Alternatives and similar repositories for Tydi-Chisel:

Users that are interested in Tydi-Chisel are comparing it to the libraries listed below

• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆39Updated 5 months ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 4 months ago
• chipsalliance / diplomacy
  ☆18Updated 2 weeks ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆45Updated 5 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆47Updated 2 months ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆28Updated this week
• sequencer / arithmetic
  ☆32Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆40Updated 2 weeks ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆28Updated 3 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• TsaiAnson / verif
  ☆11Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• pulp-platform / axi_llc
  ☆24Updated last month
• chipsalliance / OmnixtendEndpoint
  Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
  ☆17Updated 10 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last week
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆27Updated last month
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated last week
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated last year
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆43Updated last year
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆19Updated 2 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• carlosedp / chisel-playground
  Chisel HDL example applications
  ☆30Updated 2 years ago
• easysoc / layered-firrtl
  This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl
  ☆11Updated 3 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆52Updated this week