Alternatives and similar repositories for Tydi-Chisel

Users that are interested in Tydi-Chisel are comparing it to the libraries listed below

• inferablejump / bagpype
  ☆15Updated this week
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆54Updated last year
• TsaiAnson / verif
  ☆12Updated 4 years ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 4 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆52Updated last week
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆33Updated last week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated 2 months ago
• chipsalliance / diplomacy
  ☆22Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆69Updated last year
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆16Updated 11 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆33Updated 3 months ago
• chipsalliance / espresso
  ☆41Updated last week
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 3 months ago
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆40Updated this week
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• ucb-art / fft
  ☆20Updated 5 years ago
• sequencer / arithmetic
  ☆33Updated 8 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 7 months ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆50Updated 5 months ago
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆76Updated last week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆184Updated last year
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago