Alternatives and similar repositories for Tydi-Chisel

Users that are interested in Tydi-Chisel are comparing it to the libraries listed below

• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆49Updated 11 months ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• inferablejump / bagpype
  ☆15Updated last month
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang parser and library.
  ☆40Updated last week
• TsaiAnson / verif
  ☆12Updated 4 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆60Updated last week
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆30Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆66Updated 11 months ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆16Updated 9 months ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆90Updated last month
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆90Updated last week
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆46Updated 2 weeks ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated this week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 weeks ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 3 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• chipsalliance / diplomacy
  ☆21Updated 7 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆55Updated last week
• rahulk29 / sram22
  A configurable SRAM generator
  ☆54Updated last month
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆50Updated 3 months ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 11 months ago
• sequencer / arithmetic
  ☆33Updated 6 months ago
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆13Updated 6 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• ucb-bar / radiance
  ☆21Updated this week