abs-tudelft / Tydi-Chisel
☆17Updated last week
Alternatives and similar repositories for Tydi-Chisel:
Users that are interested in Tydi-Chisel are comparing it to the libraries listed below
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆39Updated 5 months ago
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- Chisel Cheatsheet☆33Updated last year
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- ☆18Updated 2 weeks ago
- ☆23Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 5 months ago
- A configurable SRAM generator☆47Updated 2 months ago
- 21st century electronic design automation tools, written in Rust.☆28Updated this week
- ☆32Updated last week
- (System)Verilog to Chisel translator☆112Updated 2 years ago
- An automatic clock gating utility☆45Updated 8 months ago
- Equivalence checking with Yosys☆40Updated 2 weeks ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 3 years ago
- ☆17Updated 2 years ago
- ☆11Updated 3 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- ☆24Updated last month
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆17Updated 10 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last month
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- Intel Compiler for SystemC☆23Updated last year
- Re-coded Xilinx primitives for Verilator use☆43Updated last year
- Simple UVM environment for experimenting with Verilator.☆19Updated 2 months ago
- Hardware generator debugger☆73Updated last year
- Chisel HDL example applications☆30Updated 2 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- The specification for the FIRRTL language☆52Updated this week