carlosedp / chiselvLinks
A RISC-V Core (RV32I) written in Chisel HDL
☆106Updated last month
Alternatives and similar repositories for chiselv
Users that are interested in chiselv are comparing it to the libraries listed below
Sorting:
- RiscyOO: RISC-V Out-of-Order Processor☆169Updated 5 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆190Updated 3 months ago
- Generic Register Interface (contains various adapters)☆134Updated last month
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆195Updated last week
- The multi-core cluster of a PULP system.☆111Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆252Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆153Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- A Tiny Processor Core☆114Updated 6 months ago
- RISC-V Verification Interface☆136Updated last month
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Chisel Learning Journey☆111Updated 2 years ago
- ☆87Updated this week
- ☆192Updated 2 years ago
- A teaching-focused RISC-V CPU design used at UC Davis☆153Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆76Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Provides various testers for chisel users☆100Updated 3 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆223Updated 2 months ago
- RISC-V System on Chip Template☆160Updated 4 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆134Updated this week
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- chipyard in mill :P☆77Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Updated last year
- Open-source high-performance non-blocking cache☆92Updated last month