carlosedp / chiselv
A RISC-V Core (RV32I) written in Chisel HDL
☆104Updated last month
Alternatives and similar repositories for chiselv:
Users that are interested in chiselv are comparing it to the libraries listed below
- A teaching-focused RISC-V CPU design used at UC Davis☆149Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- Generic Register Interface (contains various adapters)☆116Updated 7 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- The multi-core cluster of a PULP system.☆90Updated last week
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆152Updated this week
- Open-source high-performance non-blocking cache☆80Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆146Updated last week
- RISC-V Verification Interface☆89Updated 2 months ago
- Open source high performance IEEE-754 floating unit☆70Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 8 months ago
- Provides various testers for chisel users☆100Updated 2 years ago
- Simple runtime for Pulp platforms☆45Updated last month
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- ☆92Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆54Updated last year
- ☆84Updated this week
- (System)Verilog to Chisel translator☆113Updated 2 years ago
- Vector Acceleration IP core for RISC-V*☆177Updated 2 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆231Updated 6 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆145Updated 6 months ago
- Chisel Learning Journey☆109Updated 2 years ago
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆156Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- A Tiny Processor Core☆108Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆96Updated this week