Alternatives and similar repositories for chiselv:

Users that are interested in chiselv are comparing it to the libraries listed below

• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆68Updated last week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆103Updated 4 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆139Updated 3 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆65Updated 9 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆101Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆73Updated this week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆136Updated this week
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆58Updated 2 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆204Updated 2 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆86Updated last week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆144Updated 2 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆84Updated 4 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 2 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆220Updated this week
• ucb-bar / testchipip
  ☆82Updated 3 weeks ago
• chipsalliance / uvm-verilator
  ☆82Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆116Updated 3 weeks ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• riscv-software-src / riscof
  ☆70Updated 3 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆238Updated 2 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆57Updated 2 months ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆156Updated this week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆108Updated 6 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆64Updated this week