schoeberl / chisel-examplesLinks
Chisel examples and code snippets
☆266Updated 3 years ago
Alternatives and similar repositories for chisel-examples
Users that are interested in chisel-examples are comparing it to the libraries listed below
Sorting:
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆223Updated this week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Updated last year
- ☆367Updated 4 months ago
- A Library of Chisel3 Tools for Digital Signal Processing☆244Updated last year
- RISC-V Torture Test☆212Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆226Updated 3 months ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆603Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Updated 3 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆223Updated 5 years ago
- Provides various testers for chisel users☆100Updated 3 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆485Updated 2 months ago
- A dynamic verification library for Chisel.☆160Updated last year
- Instruction Set Generator initially contributed by Futurewei☆305Updated 2 years ago
- Labs to learn SpinalHDL☆153Updated last year
- A template project for beginning new Chisel work☆689Updated last week
- A basic SpinalHDL project☆89Updated 5 months ago
- ☆220Updated 7 months ago
- Run rocket-chip on FPGA☆77Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆265Updated last week
- ☆306Updated 2 weeks ago
- Verilog Configurable Cache☆192Updated last week
- ☆71Updated this week
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆334Updated 2 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆171Updated this week
- SpinalHDL-tutorial based on Jupyter Notebook☆151Updated last year
- VeeR EL2 Core☆316Updated last month