schoeberl / chisel-examples
Chisel examples and code snippets
☆246Updated 2 years ago
Alternatives and similar repositories for chisel-examples:
Users that are interested in chisel-examples are comparing it to the libraries listed below
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆190Updated last week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 7 months ago
- A Library of Chisel3 Tools for Digital Signal Processing☆234Updated 10 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆563Updated 7 months ago
- ☆311Updated 6 months ago
- Provides various testers for chisel users☆100Updated 2 years ago
- A template project for beginning new Chisel work☆623Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆186Updated last week
- Instruction Set Generator initially contributed by Futurewei☆273Updated last year
- Wrapper for Rocket-Chip on FPGAs☆129Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆118Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Chisel Learning Journey☆108Updated last year
- Labs to learn SpinalHDL☆147Updated 8 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- VeeR EL2 Core☆266Updated this week
- SpinalHDL-tutorial based on Jupyter Notebook☆132Updated 9 months ago
- Comment on the rocket-chip source code☆174Updated 6 years ago
- RISC-V Torture Test☆183Updated 8 months ago
- Digital Design with Chisel☆813Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆460Updated last month
- A dynamic verification library for Chisel.☆146Updated 4 months ago
- Network on Chip Implementation written in SytemVerilog☆169Updated 2 years ago
- ☆279Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆409Updated this week
- Chisel/Firrtl execution engine☆153Updated 6 months ago
- ☆127Updated 3 weeks ago
- Verilog Configurable Cache☆173Updated 3 months ago
- Common SystemVerilog components☆587Updated 2 weeks ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆150Updated last year