Alternatives and similar repositories for chisel-examples

Users that are interested in chisel-examples are comparing it to the libraries listed below

• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆217Updated last month
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated last year
• ucb-bar / berkeley-hardfloat
  ☆359Updated 3 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆204Updated last year
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆242Updated last year
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆223Updated last month
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆602Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆159Updated last year
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆675Updated 3 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆187Updated 2 weeks ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• RV-BOSC / OpenNoC
  ☆214Updated 5 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆165Updated this week
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆151Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated 2 years ago
• SpinalHDL / NaxRiscv
  ☆301Updated last month
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆477Updated 3 weeks ago
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆88Updated 4 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆251Updated last week
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆147Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆131Updated 5 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆263Updated 7 months ago
• OSCPU / chisel-playground
  ☆68Updated 10 months ago