Alternatives and similar repositories for DFHDL

Users that are interested in DFHDL are comparing it to the libraries listed below

• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated 2 months ago
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆16Updated last week
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆49Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆242Updated last year
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 11 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• ucb-bar / testchipip
  ☆87Updated last week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆63Updated last week
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated 3 weeks ago
• chipsalliance / diplomacy
  ☆22Updated 3 weeks ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆49Updated 2 years ago
• schoeberl / wildcat
  An implementation of RISC-V
  ☆46Updated 2 weeks ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆55Updated last year
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆105Updated last month
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 months ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 4 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 6 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆184Updated last year
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• abs-tudelft / Tydi-Chisel
  ☆20Updated 3 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago