Alternatives and similar repositories for DFHDL

Users that are interested in DFHDL are comparing it to the libraries listed below

• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 9 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆56Updated this week
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated last month
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆43Updated 7 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated last month
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆124Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆48Updated 2 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆236Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆159Updated 11 months ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆19Updated 4 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆36Updated this week
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆14Updated 4 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆86Updated last month
• schoeberl / wildcat
  An implementation of RISC-V
  ☆33Updated last week
• ucb-bar / testchipip
  ☆84Updated 3 weeks ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆178Updated 3 weeks ago
• chipsalliance / espresso
  ☆39Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 weeks ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆94Updated 2 weeks ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆120Updated 2 weeks ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago