DFiantHDL / DFHDLLinks
DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
☆88Updated last week
Alternatives and similar repositories for DFHDL
Users that are interested in DFHDL are comparing it to the libraries listed below
Sorting:
- Chisel/Firrtl execution engine☆153Updated last year
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆239Updated last year
- A Rocket-based RISC-V superscalar in-order core☆35Updated 3 months ago
- A Scala library for Context-Dependent Environments☆47Updated last year
- A scala based simulator for circuits described by a LoFirrtl file☆50Updated 2 years ago
- Chisel Fixed-Point Arithmetic Library☆14Updated 7 months ago
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆21Updated 7 months ago
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- The specification for the FIRRTL language☆63Updated last week
- ☆21Updated 5 months ago
- high-performance RTL simulator☆173Updated last year
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆48Updated last week
- ☆85Updated 2 months ago
- Vector Acceleration IP core for RISC-V*☆182Updated 3 months ago
- Useful utilities for BAR projects☆32Updated last year
- Chisel components for FPGA projects☆126Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- The home of the Chisel3 website☆21Updated last year
- A prototype GUI for chisel-development☆52Updated 5 years ago
- chipyard in mill :P☆78Updated last year
- ☆12Updated 4 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆48Updated 9 months ago
- An implementation of RISC-V☆38Updated last month
- Chisel HDL example applications☆30Updated 3 years ago
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated last week
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago