Alternatives and similar repositories for DFHDL

Users that are interested in DFHDL are comparing it to the libraries listed below

• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆155Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆244Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆123Updated 2 years ago
• schoeberl / wildcat
  An implementation of RISC-V
  ☆47Updated last month
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆38Updated 4 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• ucb-bar / testchipip
  ☆87Updated last week
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆49Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated 3 weeks ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆50Updated last year
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 6 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 3 years ago
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆18Updated last month
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated 2 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• chipsalliance / diplomacy
  ☆23Updated 2 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆186Updated last year
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆107Updated this week
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆65Updated this week
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆24Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆56Updated last year
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 4 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 6 months ago
• BSVLang / Main
  Main page
  ☆129Updated 5 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆178Updated 2 weeks ago