freechipsproject / chisel-cheatsheetLinks
Chisel Cheatsheet
☆34Updated 2 years ago
Alternatives and similar repositories for chisel-cheatsheet
Users that are interested in chisel-cheatsheet are comparing it to the libraries listed below
Sorting:
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆80Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆80Updated last year
- Intel Compiler for SystemC☆25Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ☆50Updated last month
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- A prototype GUI for chisel-development☆51Updated 5 years ago
- Provides various testers for chisel users☆99Updated 2 years ago
- Simple UVM environment for experimenting with Verilator.☆27Updated last month
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- RISC-V Virtual Prototype☆44Updated 4 years ago
- Platform Level Interrupt Controller☆43Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- A Rocket-based RISC-V superscalar in-order core☆35Updated 2 weeks ago
- chipyard in mill :P☆77Updated last year
- pulp_soc is the core building component of PULP based SoCs☆81Updated 7 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆105Updated 2 months ago
- ☆99Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year