freechipsproject / chisel-cheatsheetLinks
Chisel Cheatsheet
☆33Updated 2 years ago
Alternatives and similar repositories for chisel-cheatsheet
Users that are interested in chisel-cheatsheet are comparing it to the libraries listed below
Sorting:
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- ☆61Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- ☆29Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆55Updated 3 years ago
- ☆33Updated 2 months ago
- Intel Compiler for SystemC☆23Updated 2 years ago
- (System)Verilog to Chisel translator☆114Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- ☆39Updated last year
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated last month
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 3 weeks ago
- Advanced Architecture Labs with CVA6☆61Updated last year
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- Platform Level Interrupt Controller☆40Updated last year
- A configurable SRAM generator☆50Updated last week
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- ☆46Updated 3 weeks ago