Alternatives and similar repositories for vroom:

Users that are interested in vroom are comparing it to the libraries listed below

• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆390Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆658Updated last week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆614Updated 7 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆369Updated last month
• SpinalHDL / NaxRiscv
  ☆275Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆846Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆229Updated last week
• antonblanchard / microwatt
  A tiny Open POWER ISA softcore written in VHDL 2008
  ☆669Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆455Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,486Updated 3 weeks ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆310Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆244Updated this week
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆208Updated 10 months ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆317Updated 3 years ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆284Updated this week
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆231Updated this week
• riscv-non-isa / riscv-arch-test
  ☆537Updated this week
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆362Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆221Updated 3 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆219Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆225Updated 2 years ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆625Updated this week
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,038Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆572Updated 2 weeks ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆397Updated 2 years ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆205Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆308Updated 8 months ago
• litex-hub / litex-boards
  LiteX boards files
  ☆388Updated this week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆426Updated last week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆157Updated last month