Alternatives and similar repositories for vroom

Users that are interested in vroom are comparing it to the libraries listed below

• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆701Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆878Updated 2 years ago
• openpower-cores / a2i
  ☆247Updated 2 years ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆636Updated 3 weeks ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆653Updated this week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆414Updated last week
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆368Updated last year
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆706Updated last week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆323Updated 3 years ago
• SpinalHDL / NaxRiscv
  ☆287Updated 2 months ago
• antonblanchard / microwatt
  A tiny Open POWER ISA softcore written in VHDL 2008
  ☆685Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,409Updated 3 months ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆236Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆497Updated 3 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆388Updated 4 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆380Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆269Updated 3 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,589Updated 2 weeks ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆220Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆630Updated 2 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆325Updated 11 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆455Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆623Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆237Updated 6 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated 2 weeks ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,080Updated 2 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 6 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆257Updated 2 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆564Updated 3 weeks ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆224Updated last year