VRoom! RISC-V CPU
☆522Sep 2, 2024Updated last year
Alternatives and similar repositories for vroom
Users that are interested in vroom are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,189Jul 15, 2026Updated last week
- A Linux-capable RISC-V multicore for and by the world☆823Jul 13, 2026Updated last week
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆228Feb 19, 2026Updated 5 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆301Jun 16, 2026Updated last month
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SERV - The SErial RISC-V CPU☆1,836Jul 10, 2026Updated 2 weeks ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆260Jul 17, 2026Updated last week
- A simple superscalar out-of-order RISC-V microprocessor☆254Feb 24, 2025Updated last year
- 32-bit Superscalar RISC-V CPU☆1,283Sep 18, 2021Updated 4 years ago
- VeeR EH1 core☆959Jul 16, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,030Updated this week
- ☆2,167Updated this week
- ☆33Nov 25, 2022Updated 3 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,201Updated this week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- VeeR EH2 core☆274Updated this week
- GPGPU microprocessor architecture☆2,211Nov 8, 2024Updated last year
- OpenXuantie - OpenC910 Core☆1,459Jun 28, 2024Updated 2 years ago
- ☆323Jan 23, 2026Updated 6 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆624Updated this week
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,354Nov 22, 2024Updated last year
- high-performance RTL simulator☆195Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,267May 29, 2026Updated last month
- Build your hardware, easily!☆4,009Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The OpenPiton Platform☆803Feb 25, 2026Updated 4 months ago
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,428Jun 18, 2026Updated last month
- VeeR EL2 Core☆342Updated this week
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,188Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆531Jun 8, 2026Updated last month
- A dynamic verification library for Chisel.☆163Nov 9, 2024Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 3 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆251Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,201Feb 11, 2026Updated 5 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,589May 12, 2026Updated 2 months ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆323Updated this week
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,609Nov 18, 2025Updated 8 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆585Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 8 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆990Nov 15, 2024Updated last year
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago