AI-Vector-Accelerator / ava-core
A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
☆31Updated 3 years ago
Alternatives and similar repositories for ava-core:
Users that are interested in ava-core are comparing it to the libraries listed below
- DUTH RISC-V Superscalar Microprocessor☆29Updated 2 months ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- ☆24Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated 3 weeks ago
- ☆21Updated last week
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 3 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated 3 months ago
- Basic floating-point components for RISC-V processors☆63Updated 5 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆43Updated 2 months ago
- ☆25Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 6 months ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- ☆40Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆25Updated this week
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 4 months ago
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 4 months ago
- ☆18Updated 4 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆12Updated 5 months ago