AI-Vector-Accelerator / ava-core
A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
☆34Updated 4 years ago
Alternatives and similar repositories for ava-core
Users that are interested in ava-core are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆56Updated 3 months ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Platform Level Interrupt Controller☆40Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated this week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- ☆61Updated this week
- ☆27Updated last month
- Reconfigurable Binary Engine☆16Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- The multi-core cluster of a PULP system.☆92Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated last week
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 6 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆63Updated 11 months ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆24Updated this week
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 6 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆40Updated 2 years ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated 3 weeks ago
- An automatic clock gating utility☆47Updated last month
- AXI X-Bar☆19Updated 5 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago