A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
☆46Jan 31, 2026Updated last month
Alternatives and similar repositories for rvv-bench-results
Users that are interested in rvv-bench-results are comparing it to the libraries listed below
Sorting:
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆144Jan 27, 2026Updated last month
- An optimized neural network operator library for chips base on Xuantie CPU.☆98Feb 10, 2026Updated 3 weeks ago
- RiVEC Bencmark Suite☆128Nov 27, 2024Updated last year
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆13Jan 7, 2023Updated 3 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Feb 10, 2026Updated 3 weeks ago
- The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.☆44Oct 25, 2021Updated 4 years ago
- ☆14Feb 28, 2023Updated 3 years ago
- ☆17Jul 31, 2021Updated 4 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆235Jan 14, 2026Updated last month
- Intel Compiler for SystemC☆29Jun 1, 2023Updated 2 years ago
- ☆27Oct 25, 2021Updated 4 years ago
- ☆35Jun 9, 2022Updated 3 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Mar 26, 2024Updated last year
- Apache NuttX RTOS for Pine64 Star64 64-bit RISC-V SBC (StarFive JH7110)☆32Updated this week
- RISC-V Online Help☆36Aug 13, 2025Updated 6 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Jan 19, 2026Updated last month
- This project contains a code generator that produces static C NN inference deployment code targeting tiny micro-controllers (TinyML) as r…☆30Sep 22, 2021Updated 4 years ago
- Example for running IREE in a bare-metal Arm environment.☆40Feb 24, 2026Updated last week
- PLCT实验室 V8 for RISC-V 的主仓库。2020年完成部署。☆24Jul 25, 2020Updated 5 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆38Dec 23, 2021Updated 4 years ago
- A sphinx extension that allows including wavedrom diagrams by using its text-based representation☆39Sep 3, 2024Updated last year
- Kinematic and dynamic models of continuum and articulated soft robots.☆15Nov 22, 2025Updated 3 months ago
- ☆19Feb 5, 2026Updated last month
- Digital Signal Processing and Well-Known Modulations on HDL☆41May 22, 2025Updated 9 months ago
- Self-Tuning Adaptive Radix Tree☆30Apr 19, 2020Updated 5 years ago
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆108Apr 12, 2025Updated 10 months ago
- A baremetal experiment of Allwinner D1, without FEL☆33May 4, 2023Updated 2 years ago
- ☆161Jan 4, 2026Updated 2 months ago
- buildroot fork☆38Nov 16, 2025Updated 3 months ago
- MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems☆12Jun 20, 2024Updated last year
- Airfoil Library created with Xoptfoil2☆11Jan 10, 2026Updated 2 months ago
- A linearizability checker for concurrent data structures☆12Aug 3, 2023Updated 2 years ago
- ☆14Apr 14, 2025Updated 10 months ago
- [ACL 2025] Squeezed Attention: Accelerating Long Prompt LLM Inference☆57Nov 20, 2024Updated last year
- ☆10Nov 1, 2021Updated 4 years ago
- Schema-aware JSON compression with millisecond lookups — cut transfer/storage while enabling exists*/pos* queries. (Demo + wheels; core i…☆24Feb 21, 2026Updated 2 weeks ago
- Sandbox that demonstrates derivation of camera Log to Linear conversions, and an ACES IDT and ODT for Z-Log 2.☆10Nov 14, 2021Updated 4 years ago
- ☆10Sep 10, 2023Updated 2 years ago