A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
☆51Aug 24, 2026Updated 2 months ago
Alternatives and similar repositories for rvv-bench-results
Users that are interested in rvv-bench-results are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆155Aug 14, 2026Updated 2 months ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆105Feb 10, 2026Updated 8 months ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆31Feb 10, 2026Updated 8 months ago
- Nuclei RISC-V Linux Software Development Kit☆61Oct 12, 2026Updated 2 weeks ago
- Port of the xv6 OS to the VisionFive 2 RISC V board☆25Mar 26, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RiVEC Bencmark Suite☆134Nov 27, 2024Updated last year
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- ☆14Feb 28, 2023Updated 3 years ago
- This repo hold information on the open-standard OVP APIs☆21Dec 11, 2025Updated 10 months ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆107Updated this week
- VCD Parser for Node.js☆11Jan 7, 2023Updated 3 years ago
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆13Jan 7, 2023Updated 3 years ago
- Apache NuttX RTOS for Pine64 Star64 64-bit RISC-V SBC (StarFive JH7110)☆31Updated this week
- ☆14Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆44Apr 25, 2026Updated 6 months ago
- RISC-V soft-core PEs for TaPaSCo☆24Jul 24, 2026Updated 3 months ago
- Administrative repository for the Integrated Matrix Extension Task Group☆39Jul 27, 2026Updated 3 months ago
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆22Nov 20, 2025Updated 11 months ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆39Mar 26, 2024Updated 2 years ago
- KVM RISC-V HowTOs☆48Jun 9, 2022Updated 4 years ago
- Nuclei RISC-V Software Development Kit☆168Oct 14, 2026Updated 2 weeks ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆264Oct 12, 2026Updated 2 weeks ago
- Codeplay's tutorial LLDB-MSP430 - as presented at the 2016 EuroLLVM Developers' Meeting in Barcelona.☆10Mar 15, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆12Nov 4, 2023Updated 2 years ago
- Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization☆25Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆74Jun 28, 2025Updated last year
- ☆11May 3, 2026Updated 5 months ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- LLVM OpenCL C compiler suite for ventus GPGPU☆64Oct 13, 2026Updated 2 weeks ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- ☆18Jul 31, 2021Updated 5 years ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆60Dec 19, 2023Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆20Oct 19, 2026Updated last week
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆43Aug 15, 2025Updated last year
- Administrative repository for the Attached Matrix Facility Task Group☆15Dec 11, 2023Updated 2 years ago
- Some knowledge about riscv rvv1.0，include rvv intrinsic examples☆18Oct 24, 2026Updated last week
- Unit tests generator for RVV 1.0☆118May 25, 2026Updated 5 months ago
- ☆34Jul 21, 2026Updated 3 months ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆31Apr 24, 2025Updated last year