Alternatives and similar repositories for rvv-bench-results

Users that are interested in rvv-bench-results are comparing it to the libraries listed below

• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆120Updated 3 weeks ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆59Updated last week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆106Updated 2 months ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆46Updated last year
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆173Updated last week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 2 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆145Updated 2 months ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆181Updated 2 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆143Updated this week
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆38Updated this week
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆113Updated this week
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated 3 weeks ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• tenstorrent / whisper
  ☆52Updated 2 weeks ago
• pulp-platform / redmule
  ☆71Updated this week
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆46Updated last week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆168Updated last week
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated 2 weeks ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆34Updated 3 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆159Updated 5 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆110Updated last year
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆39Updated 4 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆35Updated 2 years ago
• vortexgpgpu / skybox
  Vortex Graphics
  ☆80Updated 10 months ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆37Updated 3 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago