camel-cdr / rvv-bench-results
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
☆31Updated last week
Alternatives and similar repositories for rvv-bench-results:
Users that are interested in rvv-bench-results are comparing it to the libraries listed below
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆110Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆93Updated last week
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- The specification for the FIRRTL language☆54Updated this week
- This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW p…☆29Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week
- Chisel library for Unum Type-III Posit Arithmetic☆37Updated 3 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated 9 months ago
- A tiny RISC-V instruction decoder and instruction set simulator☆19Updated 10 months ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- ☆131Updated last year
- high-performance RTL simulator☆156Updated 10 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated last week
- Main page☆126Updated 5 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆150Updated last week
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- RISC-V Formal Verification Framework☆133Updated last week
- Documentation for the BOOM processor☆47Updated 8 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- RISC-V architecture concurrency model litmus tests☆77Updated last year
- Vector Acceleration IP core for RISC-V*☆176Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆39Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆95Updated last month
- ☆42Updated 3 years ago
- ☆150Updated last year
- ☆41Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆156Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Mutation Cover with Yosys (MCY)☆80Updated this week