scarv / scarv-cpu
SCARV: a side-channel hardened RISC-V platform
☆26Updated 2 years ago
Alternatives and similar repositories for scarv-cpu
Users that are interested in scarv-cpu are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated this week
- Platform Level Interrupt Controller☆40Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago
- ☆27Updated last month
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆29Updated 4 years ago
- ☆18Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 10 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆56Updated 3 months ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 11 months ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated last week
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- ☆36Updated 2 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆12Updated 2 months ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆17Updated 2 months ago
- Andes Vector Extension support added to riscv-dv☆16Updated 4 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- ☆25Updated 2 months ago