scarv / scarv-cpuLinks
SCARV: a side-channel hardened RISC-V platform
☆27Updated 2 years ago
Alternatives and similar repositories for scarv-cpu
Users that are interested in scarv-cpu are comparing it to the libraries listed below
Sorting:
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- ☆33Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- RISC-V IOMMU in verilog☆20Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- ☆20Updated last month
- Mutation Cover with Yosys (MCY)☆88Updated 3 weeks ago
- ☆18Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Advanced Debug Interface☆14Updated 10 months ago
- Source-Opened RISCV for Crypto☆18Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago