scarv / scarv-cpuLinks
SCARV: a side-channel hardened RISC-V platform
☆27Updated 2 years ago
Alternatives and similar repositories for scarv-cpu
Users that are interested in scarv-cpu are comparing it to the libraries listed below
Sorting:
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- An Open Source Link Protocol and Controller☆25Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- ☆18Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 6 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- LIS Network-on-Chip Implementation☆31Updated 8 years ago
- Source-Opened RISCV for Crypto☆16Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆33Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- ☆17Updated 3 weeks ago
- A DMA Controller for RISCV CPUs☆14Updated 10 years ago
- Simple UVM environment for experimenting with Verilator.☆23Updated 3 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 7 months ago
- SCARV: a side-channel hardened RISC-V platform☆20Updated 4 years ago
- Advanced Debug Interface☆15Updated 7 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago