Alternatives and similar repositories for riscv-matrix-project

Users that are interested in riscv-matrix-project are comparing it to the libraries listed below

• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆156Updated 11 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆223Updated 2 months ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆135Updated 10 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆133Updated 5 years ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆24Updated last year
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆149Updated this week
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆206Updated 5 years ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆328Updated 3 weeks ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆127Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆99Updated 2 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆72Updated last year
• ucb-bar / uciedigital
  An open-source UCIe controller implementation
  ☆81Updated this week
• hyoukjun / OpenSMART
  Public release
  ☆58Updated 6 years ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆165Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 9 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆257Updated 3 weeks ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆81Updated 4 months ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆79Updated this week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• riscv-admin / integrated-matrix-extension
  Administrative repository for the Integrated Matrix Extension Task Group
  ☆30Updated 3 weeks ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆37Updated 2 months ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆27Updated 2 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆76Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆201Updated 4 months ago
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆255Updated 3 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago