riscv-stc / riscv-matrix-projectLinks
Top project for RISC-V Matrix extension proposal and related opensource implementations.
☆35Updated last year
Alternatives and similar repositories for riscv-matrix-project
Users that are interested in riscv-matrix-project are comparing it to the libraries listed below
Sorting:
- A matrix extension proposal for AI applications under RISC-V architecture☆161Updated 11 months ago
- A Chisel RTL generator for network-on-chip interconnects☆225Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆138Updated 11 months ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆333Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated last week
- RISC-V Matrix Specification☆23Updated last year
- A Fast, Low-Overhead On-chip Network☆265Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆166Updated 2 years ago
- An open-source UCIe implementation☆82Updated this week
- An integrated CGRA design framework☆91Updated 10 months ago
- ☆66Updated 3 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆236Updated 3 years ago
- RiVEC Bencmark Suite☆127Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- Public release☆58Updated 6 years ago
- Unit tests generator for RVV 1.0☆100Updated 2 months ago
- ☆58Updated 6 years ago
- some knowleage about SystemC/TLM etc.☆27Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- ☆219Updated 7 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆206Updated 5 years ago
- ☆12Updated 3 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆31Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago