Top project for RISC-V Matrix extension proposal and related opensource implementations.
☆35Mar 26, 2024Updated last year
Alternatives and similar repositories for riscv-matrix-project
Users that are interested in riscv-matrix-project are comparing it to the libraries listed below
Sorting:
- RISC-V Matrix Specification☆23Dec 2, 2024Updated last year
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- Unlimited Vector Extension with Data Streaming Support☆12Nov 25, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆12Jan 14, 2026Updated last month
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆235Jan 14, 2026Updated last month
- A Rocket-based RISC-V superscalar in-order core☆38Feb 24, 2026Updated last week
- Qingnang Smart Diagnosis is an end-to-end AI healthcare framework with field-proven application capabilities, designed to provide efficie…☆15Nov 11, 2025Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated this week
- CSiBE☆34Feb 17, 2022Updated 4 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆39Mar 7, 2025Updated last year
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆94Oct 6, 2025Updated 5 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆497Updated this week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆46Jan 31, 2026Updated last month
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆108Apr 12, 2025Updated 10 months ago
- Unit tests generator for RVV 1.0☆103Nov 11, 2025Updated 3 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆164Feb 11, 2025Updated last year
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code(使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 2 years ago
- OpenCCA: An Open Framework to Enable Arm CCA Research☆21Sep 10, 2025Updated 5 months ago
- The artifact for NDSS '25 paper "ASGARD: Protecting On-Device Deep Neural Networks with Virtualization-Based Trusted Execution Environmen…☆15Oct 16, 2025Updated 4 months ago
- The frontend app of Mailcow's CowUI web interface☆12Apr 29, 2024Updated last year
- Learn NVDLA by SOMNIA☆42Dec 13, 2019Updated 6 years ago
- ☆364Feb 24, 2026Updated last week
- ☆258Dec 22, 2022Updated 3 years ago
- ☆91Oct 18, 2023Updated 2 years ago
- Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.☆45Sep 1, 2025Updated 6 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- ☆29Oct 25, 2025Updated 4 months ago
- Official code base of the BEVDet series .☆11Oct 9, 2022Updated 3 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆12Jan 18, 2016Updated 10 years ago
- VNEC: A Vectorized Non-Empty Column Format for SpMV on cross-platform multicore CPUs☆10Feb 6, 2024Updated 2 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- A simple baremetal program template for RISC-V inspired from riscv benchmark tests☆11Apr 17, 2018Updated 7 years ago
- [ICCV 2025] Official implementation of the paper "Beyond RGB: Adaptive Parallel Processing for RAW Object Detection"☆21Oct 8, 2025Updated 5 months ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆12Jul 1, 2024Updated last year
- Final year research project to design a programmable virtual switch based on the specifications of a TSN to be implemented on a TSN netwo…☆13Nov 17, 2020Updated 5 years ago
- A standalone CXL-enabled system simulator.☆19Jan 10, 2026Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆136Feb 25, 2026Updated last week
- Documentation for RISC-V Spike☆104Oct 18, 2018Updated 7 years ago