Alternatives and similar repositories for riscv-vp-plusplus

Users that are interested in riscv-vp-plusplus are comparing it to the libraries listed below

• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆45Updated 4 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last week
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆32Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆32Updated last week
• esa-tu-darmstadt / SCAIE-V-2.0
  ☆20Updated last month
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆71Updated last year
• pulp-platform / redmule
  ☆89Updated last week
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆125Updated last week
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆33Updated 8 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆25Updated 6 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• gvsoc / gvsoc
  ☆35Updated this week
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated last month
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆61Updated 4 years ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆25Updated last week
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆38Updated 4 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆29Updated 4 years ago
• riscv-admin / integrated-matrix-extension
  Administrative repository for the Integrated Matrix Extension Task Group
  ☆30Updated last week
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆33Updated 3 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆89Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• hyoukjun / OpenSMART
  Public release
  ☆58Updated 6 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆71Updated 3 weeks ago
• pulp-platform / axi_llc
  ☆32Updated 3 weeks ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆34Updated 5 years ago