ics-jku / riscv-vp-plusplusLinks
RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.
☆47Updated 3 weeks ago
Alternatives and similar repositories for riscv-vp-plusplus
Users that are interested in riscv-vp-plusplus are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- Administrative repository for the Integrated Matrix Extension Task Group☆30Updated this week
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- RISC-V Virtual Prototype☆44Updated 4 years ago
- matrix-coprocessor for RISC-V☆25Updated 7 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 weeks ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last week
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- ☆20Updated 2 weeks ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 6 months ago
- ☆88Updated last week
- ☆32Updated last week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆124Updated this week
- RISC-V Matrix Specification☆23Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- ☆35Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆93Updated 3 weeks ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆38Updated last month
- The OpenPiton Platform☆17Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆30Updated 2 weeks ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated this week
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago