ics-jku / riscv-vp-plusplus
RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.
☆24Updated last month
Related projects ⓘ
Alternatives and complementary repositories for riscv-vp-plusplus
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- RISC-V Virtual Prototype☆37Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated last month
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆32Updated last year
- SystemC training aimed at TLM.☆26Updated 4 years ago
- RISC-V Matrix Specification☆15Updated 2 months ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆49Updated last month
- ☆37Updated 5 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 8 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆9Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Algorithmic C Machine Learning Library☆22Updated 3 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated last month
- Ratatoskr NoC Simulator☆21Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- ☆22Updated 5 years ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆16Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago