Self checking RISC-V directed tests
☆119Jun 3, 2025Updated 9 months ago
Alternatives and similar repositories for riscv_arch_tests
Users that are interested in riscv_arch_tests are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆83Mar 19, 2026Updated last week
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆24Oct 15, 2025Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 9 months ago
- ☆29Mar 1, 2025Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆238Jan 14, 2026Updated 2 months ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆140Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆38Dec 23, 2021Updated 4 years ago
- Instruction Set Generator initially contributed by Futurewei☆307Oct 17, 2023Updated 2 years ago
- VeeR EL2 Core☆326Mar 12, 2026Updated 2 weeks ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆74Jul 19, 2024Updated last year
- Random instruction generator for RISC-V processor verification☆1,270Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆142Updated this week
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Apr 18, 2025Updated 11 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Jun 22, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- ☆1,147Updated this week
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 10 months ago
- ☆665Updated this week
- ☆153Oct 6, 2023Updated 2 years ago
- A Reconfigurable RISC-V Core for Approximate Computing☆130May 30, 2025Updated 9 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆201Mar 6, 2026Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- ☆36Nov 4, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RISC-V Nexus Trace TG documentation and reference code☆58Mar 20, 2026Updated last week
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Mar 13, 2024Updated 2 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- RISC-V Directed Test Framework and Compliance Suite, RiESCUE☆60Mar 20, 2026Updated last week
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Jan 19, 2026Updated 2 months ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- ☆21May 13, 2025Updated 10 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆666Mar 8, 2026Updated 3 weeks ago
- CROSSCON-Hypervisor, a Lightweight Hypervisor☆21Dec 19, 2025Updated 3 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆50Updated this week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆146Jan 27, 2026Updated 2 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆78Jan 2, 2021Updated 5 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 2 years ago
- ☆199Dec 14, 2023Updated 2 years ago
- ☆133Aug 14, 2025Updated 7 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆124Mar 6, 2026Updated 3 weeks ago