Alternatives and similar repositories for riscv_arch_tests:

Users that are interested in riscv_arch_tests are comparing it to the libraries listed below

• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆101Updated this week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆157Updated 2 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆110Updated 2 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated 2 weeks ago
• tenstorrent / whisper
  ☆37Updated this week
• chipsalliance / uvm-verilator
  ☆89Updated last year
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆185Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆79Updated last week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆69Updated last week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆88Updated last month
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆172Updated this week
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆70Updated this week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆158Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆170Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆140Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆83Updated last week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆84Updated 2 months ago
• bsc-loca / sargantana
  ☆86Updated 11 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆133Updated 5 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆89Updated this week
• sparcians / map
  Modeling Architectural Platform
  ☆180Updated 2 weeks ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆235Updated this week
• chipsalliance / VeeR-ISS
  ☆131Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆248Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆130Updated 2 weeks ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆69Updated 6 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆186Updated 8 months ago