tenstorrent / whisperLinks
☆52Updated 2 weeks ago
Alternatives and similar repositories for whisper
Users that are interested in whisper are comparing it to the libraries listed below
Sorting:
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated last week
- Chisel RISC-V Vector 1.0 Implementation☆106Updated 2 months ago
- Self checking RISC-V directed tests☆111Updated 2 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆98Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆173Updated last week
- ☆71Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Vector Acceleration IP core for RISC-V*☆181Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆198Updated last month
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆103Updated 2 months ago
- The multi-core cluster of a PULP system.☆105Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- high-performance RTL simulator☆168Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- ☆105Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆171Updated 3 weeks ago
- Administrative repository for the Integrated Matrix Extension Task Group☆26Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Unit tests generator for RVV 1.0☆89Updated 3 weeks ago
- RISC-V Matrix Specification☆22Updated 8 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆124Updated this week
- A Rocket-based RISC-V superscalar in-order core☆34Updated 3 months ago
- matrix-coprocessor for RISC-V☆19Updated 3 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆85Updated 2 months ago