tenstorrent / whisper
☆37Updated last week
Alternatives and similar repositories for whisper:
Users that are interested in whisper are comparing it to the libraries listed below
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Self checking RISC-V directed tests☆102Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆101Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆88Updated last month
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆35Updated 3 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆89Updated this week
- ☆53Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆69Updated last week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆157Updated 2 months ago
- Unit tests generator for RVV 1.0☆79Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 10 months ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- ☆89Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- The specification for the FIRRTL language☆52Updated this week
- pulp_soc is the core building component of PULP based SoCs☆79Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆89Updated 3 weeks ago
- RISC-V Matrix Specification☆19Updated 3 months ago
- ☆33Updated 8 months ago
- (System)Verilog to Chisel translator☆112Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆71Updated this week
- ☆86Updated 11 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆97Updated last year
- A Fast, Low-Overhead On-chip Network☆185Updated this week
- For contributions of Chisel IP to the chisel community.☆60Updated 4 months ago