Alternatives and similar repositories for whisper:

Users that are interested in whisper are comparing it to the libraries listed below

• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆103Updated last month
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆104Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 11 months ago
• pulp-platform / redmule
  ☆55Updated this week
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆74Updated this week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆92Updated this week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆92Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated 2 weeks ago
• chipsalliance / uvm-verilator
  ☆92Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆81Updated 2 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆189Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆61Updated 10 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆51Updated 5 years ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆160Updated 3 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 7 months ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆24Updated 7 months ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆93Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆92Updated last month
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆175Updated last week
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆99Updated last year
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆21Updated 4 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆106Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆70Updated last week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆145Updated 3 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆50Updated 2 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆71Updated 7 months ago