tenstorrent / whisperLinks
☆76Updated 3 weeks ago
Alternatives and similar repositories for whisper
Users that are interested in whisper are comparing it to the libraries listed below
Sorting:
- Self checking RISC-V directed tests☆119Updated 8 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆135Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆129Updated 4 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆224Updated 3 weeks ago
- Open-source RTL logic simulator with CUDA acceleration☆255Updated 4 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆123Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆194Updated 4 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last month
- The multi-core cluster of a PULP system.☆111Updated last month
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Administrative repository for the Integrated Matrix Extension Task Group☆32Updated last month
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆160Updated last week
- Unit tests generator for RVV 1.0☆100Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- ☆125Updated 5 months ago
- ☆90Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 3 weeks ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆119Updated 2 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Updated 8 months ago
- ☆193Updated 2 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆239Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆151Updated 2 years ago
- ☆36Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RISC-V Matrix Specification☆23Updated last year
- Modeling Architectural Platform☆216Updated this week
- A high-efficiency system-on-chip for floating-point compute workloads.☆44Updated last year