An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
☆13May 29, 2026Updated 3 months ago
Alternatives and similar repositories for chipyard
Users that are interested in chipyard are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆262Aug 18, 2026Updated 2 weeks ago
- ☆19Aug 27, 2022Updated 4 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆39Mar 26, 2024Updated 2 years ago
- ☆19Jun 8, 2026Updated 2 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- RISC-V Matrix Specification☆27Dec 2, 2024Updated last year
- ☆10Jun 4, 2021Updated 5 years ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆20Jan 29, 2026Updated 7 months ago
- A version of PicoSoc that runs from BRAM, with extra peripherals☆12Oct 26, 2019Updated 6 years ago
- Awaken spring. An entry in PyWeek 29.☆12Jan 23, 2022Updated 4 years ago
- A wishbone controlled PWM (audio) controller☆19Jan 16, 2024Updated 2 years ago
- Final year research project to design a programmable virtual switch based on the specifications of a TSN to be implemented on a TSN netwo…☆13Nov 17, 2020Updated 5 years ago
- cheriot-kudu is a 32-bit dual-issue RISC-V MCU core with CHERIoT support☆17Aug 26, 2026Updated last week
- ☆18May 1, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆16Jan 19, 2024Updated 2 years ago
- ☆16Oct 7, 2020Updated 5 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Updated this week
- rust riscv64 xv6 reimplementation☆21Dec 8, 2023Updated 2 years ago
- Tenstorrent Topology (TT-Topology) is a command line utility used to flash multiple NB cards on a system to use specific eth routing conf…☆16Jul 23, 2026Updated last month
- A Python ECS (Entity Component System)☆14Oct 5, 2024Updated last year
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- ☆12Apr 19, 2022Updated 4 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 12 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RADIX-4 SRT division☆13Oct 31, 2019Updated 6 years ago
- Time Sensitive Network and Audio-Video Bridge document collection☆30May 13, 2018Updated 8 years ago
- Yosys Plugins☆22Jul 16, 2019Updated 7 years ago
- Blackwire overview, status, roadmap and top-level documentation.☆17Aug 21, 2023Updated 3 years ago
- FocusFlow: Boosting Key-Points Optical Flow Estimation for Autonomous Driving☆11Jan 22, 2024Updated 2 years ago
- Rocket Chip Generator☆13Jul 31, 2021Updated 5 years ago
- This project implements the Titans architecture from the paper "Titans: Learning to Memorize at Test Time" for market data prediction.☆10Jan 19, 2025Updated last year
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- Cray-LM unified training and inference stack.☆22Jan 30, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- BrightEyes Time-tagging module: open-source hardware, a time to digital converter, multi channels, with a resolution of 30 ps designed fo…☆20Oct 30, 2023Updated 2 years ago
- FreeBSD src tree☆18Oct 12, 2020Updated 5 years ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆11Jul 1, 2024Updated 2 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆255Aug 27, 2026Updated last week
- Build scripts of ci.rvperf.org☆12Apr 10, 2026Updated 4 months ago
- ☆13Jun 4, 2024Updated 2 years ago
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆22Aug 23, 2018Updated 8 years ago