Alternatives and similar repositories for chipyard

Users that are interested in chipyard are comparing it to the libraries listed below

• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆165Updated 4 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆55Updated 5 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆97Updated this week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆103Updated this week
• chipsalliance / OmnixtendEndpoint
  Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
  ☆18Updated 3 weeks ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆105Updated last year
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated this week
• tenstorrent / whisper
  ☆43Updated 3 weeks ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆108Updated this week
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated last week
• embecosm / embecosm-toolchain-releases
  ☆16Updated last month
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆37Updated 3 years ago
• pulp-platform / redmule
  ☆62Updated this week
• riscv / riscv-bfloat16
  ☆35Updated 10 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆57Updated this week
• olofk / qerv
  ☆16Updated last month
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆101Updated 2 years ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆22Updated 6 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 2 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆98Updated last month
• tenstorrent / rv-core-dv-kit
  ☆25Updated 3 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 3 weeks ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• dovebutch / tlv-comp
  ☆27Updated 3 months ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 4 years ago
• pulp-platform / occamy
  A high-efficiency system-on-chip for floating-point compute workloads.
  ☆36Updated 4 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆60Updated 4 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year