Alternatives and similar repositories for chipyard

Users that are interested in chipyard are comparing it to the libraries listed below

• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆162Updated 4 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆92Updated this week
• riscv-admin / graphics
  Graphics SIG organizational information
  ☆39Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆56Updated 3 months ago
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆33Updated last year
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆105Updated 2 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆145Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• pulp-platform / redmule
  ☆61Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆47Updated 2 months ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆54Updated 4 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆97Updated this week
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆57Updated 3 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆99Updated last month
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆36Updated 3 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆97Updated last week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆102Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated last year
• zeroasiccorp / ebrick-demo
  Demo: how to create a custom EBRICK
  ☆21Updated 5 months ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆177Updated 3 weeks ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• chipsalliance / OmnixtendEndpoint
  Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
  ☆17Updated 11 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆83Updated this week
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆88Updated 5 years ago
• tenstorrent / whisper
  ☆42Updated this week