grayresearch / CX
Proposed RISC-V Composable Custom Extensions Specification
☆69Updated 9 months ago
Alternatives and similar repositories for CX:
Users that are interested in CX are comparing it to the libraries listed below
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 8 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆44Updated last month
- Platform Level Interrupt Controller☆36Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- The multi-core cluster of a PULP system.☆69Updated this week
- ☆87Updated last year
- A SystemVerilog source file pickler.☆54Updated 4 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- ☆32Updated 4 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 3 months ago
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 3 months ago
- RISC-V Nox core☆62Updated 6 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated 2 weeks ago
- SystemVerilog frontend for Yosys☆74Updated this week
- Open source ISS and logic RISC-V 32 bit project☆42Updated 2 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆34Updated 3 years ago
- ☆31Updated last month
- The OpenPiton Platform☆16Updated 6 months ago
- ☆54Updated 2 years ago
- ☆36Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 9 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- ☆59Updated 3 years ago
- 👾 Design ∪ Hardware☆74Updated 3 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆51Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Announcements related to Verilator☆39Updated 4 years ago