Proposed RISC-V Composable Custom Extensions Specification
☆70Jun 28, 2025Updated 8 months ago
Alternatives and similar repositories for CX
Users that are interested in CX are comparing it to the libraries listed below
Sorting:
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 9 months ago
- ☆14Feb 2, 2026Updated 3 weeks ago
- A Rocket-based RISC-V superscalar in-order core☆38Oct 5, 2025Updated 4 months ago
- Self checking RISC-V directed tests☆119Jun 3, 2025Updated 8 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Feb 3, 2026Updated 3 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆101Feb 20, 2026Updated last week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆234Jan 14, 2026Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Jan 5, 2025Updated last year
- ☆19Oct 28, 2024Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆138Updated this week
- Prototype for a SPIR-V assembler and dissasembler. It provides a composable Java interface for generating SPIR-V code at runtime.☆13Oct 31, 2025Updated 4 months ago
- Universal Memory Interface (UMI)☆157Feb 20, 2026Updated last week
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Updated this week
- Demo SoC for SiliconCompiler.☆62Jan 28, 2026Updated last month
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 3 months ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Updated this week
- The OpenPiton Platform☆772Updated this week
- Library of open source PDKs☆64Feb 3, 2026Updated 3 weeks ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80May 22, 2024Updated last year
- ☆11Jun 29, 2021Updated 4 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- CoreScore☆172Nov 14, 2025Updated 3 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆244May 22, 2025Updated 9 months ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆82Jan 28, 2026Updated last month
- A Linux-capable RISC-V multicore for and by the world☆769Feb 9, 2026Updated 2 weeks ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆250Feb 22, 2026Updated last week
- CPUs☆16Dec 21, 2020Updated 5 years ago
- Dual-Core Out-of-Order MIPS CPU Design☆21May 8, 2025Updated 9 months ago