grayresearch / CXLinks
Proposed RISC-V Composable Custom Extensions Specification
☆71Updated last year
Alternatives and similar repositories for CX
Users that are interested in CX are comparing it to the libraries listed below
Sorting:
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- ☆46Updated 2 months ago
- Library of open source Process Design Kits (PDKs)☆47Updated this week
- The multi-core cluster of a PULP system.☆101Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 7 months ago
- ☆59Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- A SystemVerilog source file pickler.☆57Updated 8 months ago
- RISC-V Nox core☆64Updated 2 months ago
- ☆96Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆82Updated this week
- Platform Level Interrupt Controller☆41Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 8 months ago
- An automatic clock gating utility☆49Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 3 months ago
- ☆36Updated 2 years ago
- ☆32Updated 5 months ago
- ☆27Updated this week
- ☆30Updated 2 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆64Updated last week
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆18Updated last month
- The OpenPiton Platform☆16Updated 10 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆33Updated last year