grayresearch / CX
Proposed RISC-V Composable Custom Extensions Specification
☆67Updated 6 months ago
Related projects ⓘ
Alternatives and complementary repositories for CX
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆42Updated 3 weeks ago
- ☆75Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- For contributions of Chisel IP to the chisel community.☆55Updated 2 weeks ago
- RISC-V Nox core☆61Updated 3 months ago
- ☆57Updated 3 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 5 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- Announcements related to Verilator☆38Updated 4 years ago
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- The multi-core cluster of a PULP system.☆56Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- A SystemVerilog source file pickler.☆51Updated last month
- ☆36Updated 2 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- Automatic SystemVerilog linting in github actions with the help of Verible☆28Updated 3 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- ☆39Updated 4 years ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- RISCV model for Verilator/FPGA targets☆45Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- Generic Register Interface (contains various adapters)☆100Updated last month
- ☆52Updated 2 years ago