CNN accelerator
☆30Jun 11, 2017Updated 9 years ago
Alternatives and similar repositories for cs231n-project
Users that are interested in cs231n-project are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- Advanced Debug Interface☆14Jan 23, 2025Updated last year
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- Verilog language support in Atom☆18Jun 30, 2019Updated 7 years ago
- verilog CNN generator for FPGA☆34Jan 4, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- I'm going to use the Winograd’s minimal filtering algorithms to introduce a new class of fast algorithms for convolutional neural networks…☆12Mar 22, 2018Updated 8 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Jun 3, 2019Updated 7 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 7 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 10 years ago
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 12 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- Spike with a coherence supported cache model☆14Jul 9, 2024Updated 2 years ago
- RISC-V port to Parallella Board☆13Aug 22, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RTL Verilog library for various DSP modules☆99Feb 17, 2022Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆200Dec 15, 2017Updated 8 years ago
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- A convolutional neural network implemented in hardware (verilog)☆166Sep 7, 2017Updated 8 years ago
- ☆26Updated this week
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated 10 months ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆41Mar 14, 2015Updated 11 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆11Jun 1, 2021Updated 5 years ago
- DyRACT Open Source Repository☆16May 4, 2016Updated 10 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 5 months ago
- RTL implementation of Flex-DPE.☆117Feb 22, 2020Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Jan 6, 2022Updated 4 years ago
- Magic VLSI Layout Tool☆21Oct 10, 2019Updated 6 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Software implementation of DVB-T2☆17Oct 31, 2018Updated 7 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 7 years ago
- OpenCL Labs for PAPAA Summer School 2016 Edition☆46Jul 24, 2017Updated 9 years ago
- Next generation CGRA generator☆119Jul 16, 2026Updated last week
- An automated HDC platform☆11Mar 16, 2026Updated 4 months ago
- ☆40Mar 11, 2019Updated 7 years ago
- PYNQ demo as seen at FPL 2018☆22Nov 23, 2020Updated 5 years ago