Alternatives and similar repositories for T-DLA

Users that are interested in T-DLA are comparing it to the libraries listed below

• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆52Updated last month
• Accelergy-Project / processing-in-memory-design
  ☆26Updated last year
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆47Updated 3 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• he-actlab / planaria.code
  ☆25Updated 3 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• microideax / Open-Dnn
  ☆28Updated 5 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 3 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• jinhachung / tptpu-sim
  A Toy-Purpose TPU Simulator
  ☆18Updated 11 months ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• suchandler96 / gem5-NVDLA
  ☆30Updated 2 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 5 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆19Updated 5 years ago
• harvard-acc / EdgeBERT
  HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
  ☆48Updated last year
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆36Updated 4 years ago
• Sibylau / HLS_designs
  Systolic array implementations for Cholesky, LU, and QR decomposition
  ☆42Updated 6 months ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆29Updated 3 years ago
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆27Updated last month
• union-codesign / union
  ☆14Updated 3 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 5 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆91Updated 8 months ago
• RalphMao / EIE-simulator
  C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)
  ☆22Updated 4 years ago
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆24Updated last year
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆27Updated 2 years ago