Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).
☆20Nov 18, 2018Updated 7 years ago
Alternatives and similar repositories for Convolutional-Neural-Network-Accelerator
Users that are interested in Convolutional-Neural-Network-Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 8 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆200Dec 15, 2017Updated 8 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- Code for "CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction" on CIFAR-10/100.☆14Dec 10, 2021Updated 4 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 13 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Network on Chip for MPSoC☆28Jun 16, 2026Updated last month
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件，并在 ARM＋FPGA 完成项目部署，实现通过摄取图片并通过 ARM＋FPGA 综合部署和加速识别算法，并通过显示驱动，在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆62Nov 22, 2023Updated 2 years ago
- ☆50Apr 8, 2023Updated 3 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆12Oct 17, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆14May 14, 2024Updated 2 years ago
- ☆18Feb 25, 2026Updated 4 months ago
- Training Quantized Neural Networks with a Full-precision Auxiliary Module☆13Jun 19, 2020Updated 6 years ago
- A Toy-Purpose TPU Simulator☆24Jun 7, 2024Updated 2 years ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆19Jan 17, 2026Updated 6 months ago
- ☆12Nov 28, 2024Updated last year
- ☆21Feb 5, 2020Updated 6 years ago
- A new multi-task learning framework using Vision Transformers☆11Jun 19, 2024Updated 2 years ago
- ☆14Dec 10, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 7 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- Code for "Improving Robustness of Vision Transformers by Reducing Sensitivity to Patch Corruptions"☆14Sep 3, 2023Updated 2 years ago
- [NeurIPS 2022] “M³ViT: Mixture-of-Experts Vision Transformer for Efficient Multi-task Learning with Model-Accelerator Co-design”, Hanxue …☆137Nov 30, 2022Updated 3 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆35Mar 21, 2020Updated 6 years ago
- Peking University Embedded Microprocessor System Lesson’s all Homework☆10Dec 28, 2021Updated 4 years ago
- ☆53Aug 28, 2024Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆54Sep 20, 2024Updated last year
- gem5 repository to study chiplet-based systems☆91Apr 18, 2019Updated 7 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- A bayesian approach to examining default mode network functional connectivity and cognitive performance in major depressive disorder☆13Aug 23, 2019Updated 6 years ago
- Xilinx AXI VIP example of use☆44Apr 24, 2021Updated 5 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆27Jan 11, 2019Updated 7 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆140May 10, 2024Updated 2 years ago
- ☆13Sep 24, 2023Updated 2 years ago