zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
FPGA/AES/LeNet/VGG16
☆99Updated 6 years ago
Alternatives and similar repositories for FPGA-Accelerator-for-AES-LeNet-VGG16:
Users that are interested in FPGA-Accelerator-for-AES-LeNet-VGG16 are comparing it to the libraries listed below
- An LeNet RTL implement onto FPGA☆44Updated 6 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆185Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆172Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆177Updated 7 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 6 years ago
- ☆104Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆109Updated 7 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆38Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- 中文:☆97Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆92Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆143Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 2 months ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆71Updated 6 years ago
- ☆63Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆90Updated 3 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆27Updated 4 years ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆144Updated 9 months ago
- IC implementation of Systolic Array for TPU☆207Updated 5 months ago
- Implementation of CNN using Verilog☆209Updated 7 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- Verilog implementation of Softmax function☆59Updated 2 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 2 years ago