kerryliukk / NTHU-ICLABLinks
清華大學 | 積體電路設計實驗 (IC LAB) | 110上
☆44Updated 2 years ago
Alternatives and similar repositories for NTHU-ICLAB
Users that are interested in NTHU-ICLAB are comparing it to the libraries listed below
Sorting:
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆197Updated 10 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆132Updated 4 months ago
- Convolutional Neural Network RTL-level Design☆68Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆222Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆100Updated last month
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆166Updated 5 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆62Updated 6 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆162Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆20Updated last year
- ☆115Updated 5 years ago
- ☆42Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- IC implementation of Systolic Array for TPU☆273Updated 10 months ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆187Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆160Updated last year
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆24Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆65Updated 6 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆40Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆192Updated 7 years ago
- some interesting demos for starters☆84Updated 2 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆56Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆155Updated 4 years ago
- AXI总线连接器☆103Updated 5 years ago
- 3×3脉动阵列乘法器☆47Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆16Updated 3 years ago