kerryliukk / NTHU-ICLAB
清華大學 | 積體電路設計實驗 (IC LAB) | 110上
☆33Updated 2 years ago
Alternatives and similar repositories for NTHU-ICLAB:
Users that are interested in NTHU-ICLAB are comparing it to the libraries listed below
- ☆103Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆47Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆88Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆145Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆184Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆149Updated 4 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆137Updated last year
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆13Updated 10 months ago
- IC implementation of Systolic Array for TPU☆197Updated 4 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆157Updated 11 months ago
- Deep Learning Accelerator (Convolution Neural Networks)☆176Updated 7 years ago
- AXI总线连接器☆95Updated 4 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆36Updated last week
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆172Updated 11 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆90Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆142Updated 8 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆48Updated 3 weeks ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆30Updated last year
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- CPU Design Based on RISCV ISA☆94Updated 9 months ago
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆86Updated last year
- some interesting demos for starters☆69Updated 2 years ago
- 数字IC秋招项目、手撕代码☆34Updated 10 months ago
- ☆22Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago