kerryliukk / NTHU-ICLAB
清華大學 | 積體電路設計實驗 (IC LAB) | 110上
☆24Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for NTHU-ICLAB
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆10Updated 6 months ago
- 数字IC秋招项目、手撕代码☆33Updated 6 months ago
- 2023集创赛国二,紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆119Updated last week
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆125Updated 4 months ago
- CPU Design Based on RISCV ISA☆75Updated 4 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆127Updated last year
- Convolutional Neural Network RTL-level Design☆31Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆162Updated last year
- ☆93Updated 4 years ago
- AXI总线连接器☆90Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆128Updated 4 years ago
- AXI DMA 32 / 64 bits☆97Updated 10 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆116Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆68Updated 2 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆158Updated 7 months ago
- upgrade to e203 (a risc-v core)☆37Updated 4 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆111Updated 7 months ago
- 3×3脉动阵列乘法器☆34Updated 5 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆110Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆53Updated 2 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆30Updated 2 months ago
- FFT implement by verilog_测试验证已通过☆51Updated 8 years ago
- IC Verification & SV Demo☆45Updated 3 years ago
- AXI协议规范中文翻译版☆130Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆81Updated 4 years ago
- CNN accelerator implemented with Spinal HDL☆134Updated 9 months ago
- IC implementation of Systolic Array for TPU☆148Updated 2 weeks ago
- Implementation of CNN using Verilog☆185Updated 7 years ago