StanfordAHA / ahaLinks
☆62Updated last week
Alternatives and similar repositories for aha
Users that are interested in aha are comparing it to the libraries listed below
Sorting:
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated 3 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated this week
- ☆87Updated last year
- Next generation CGRA generator☆118Updated this week
- ☆56Updated 7 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆82Updated 4 months ago
- CGRA framework with vectorization support.☆43Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆166Updated 2 years ago
- ☆62Updated 10 months ago
- CGRA Compilation Framework☆91Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆61Updated 7 months ago
- A hardware synthesis framework with multi-level paradigm☆43Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- An integrated CGRA design framework☆91Updated 10 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- ☆65Updated 9 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆58Updated 6 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Updated last month
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆41Updated 3 months ago
- ☆60Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 5 years ago
- ☆32Updated last year
- ☆109Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year