Alternatives and similar repositories for coreir

Users that are interested in coreir are comparing it to the libraries listed below

• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆109Updated 2 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆145Updated this week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆168Updated last year
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆227Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆162Updated last month
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆107Updated 9 years ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆111Updated 2 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated 3 weeks ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆117Updated this week
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆78Updated last year
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 9 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• phanrahan / magma
  magma circuits
  ☆261Updated 9 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated 3 weeks ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆103Updated 2 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 2 months ago
• lana555 / dynamatic
  ☆86Updated last year
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆60Updated this week
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆77Updated 9 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago