rdaly525 / coreirLinks
☆104Updated 3 years ago
Alternatives and similar repositories for coreir
Users that are interested in coreir are comparing it to the libraries listed below
Sorting:
- Next generation CGRA generator☆115Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆165Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 5 months ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Debuggable hardware generator☆70Updated 2 years ago
- ☆56Updated 3 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆148Updated 2 months ago
- The Task Parallel System Composer (TaPaSCo)☆110Updated 5 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆226Updated last week
- Hardware generator debugger☆76Updated last year
- A Modeling and Verification Platform for SoCs using ILAs☆79Updated last year
- high-performance RTL simulator☆180Updated last year
- ☆87Updated last year
- ILA Model Database☆24Updated 5 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- A Hardware Pipeline Description Language☆48Updated 3 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- CoreIR Symbolic Analyzer☆74Updated 4 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- Main page☆128Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆88Updated last week
- magma circuits☆262Updated last year