Alternatives and similar repositories for coreir

Users that are interested in coreir are comparing it to the libraries listed below

• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated last week
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆159Updated 11 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated 11 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 3 weeks ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆104Updated 3 weeks ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 7 months ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆104Updated 9 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆257Updated 2 weeks ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆84Updated last year
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆223Updated last week
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆157Updated last month
• phanrahan / magma
  magma circuits
  ☆261Updated 7 months ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• lana555 / dynamatic
  ☆86Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 11 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆56Updated this week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 9 months ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆281Updated 2 weeks ago