Alternatives and similar repositories for coreir:

Users that are interested in coreir are comparing it to the libraries listed below

• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated this week
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆120Updated 10 months ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆153Updated 3 weeks ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆51Updated 5 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆156Updated 10 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆75Updated 9 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆103Updated 5 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• StanfordAHA / aha
  ☆57Updated this week
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆82Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆220Updated this week
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 10 years ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆108Updated this week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last week
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 8 months ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆103Updated 9 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 6 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆56Updated 3 months ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• lana555 / dynamatic
  ☆86Updated last year
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆53Updated this week
• phanrahan / magma
  magma circuits
  ☆259Updated 6 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago