zslwyuan / Light-HLSLinks
Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
☆62Updated 3 years ago
Alternatives and similar repositories for Light-HLS
Users that are interested in Light-HLS are comparing it to the libraries listed below
Sorting:
- DASS HLS Compiler☆29Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- A hardware synthesis framework with multi-level paradigm☆42Updated 11 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆148Updated last week
- An integrated CGRA design framework☆91Updated 8 months ago
- ☆15Updated last month
- ☆87Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆61Updated this week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- An infrastructure for integrated EDA☆42Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆168Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- ☆17Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆80Updated 2 weeks ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆52Updated 2 years ago
- ☆60Updated 2 years ago
- Dataset for ML-guided Accelerator Design☆42Updated last year
- ☆72Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 5 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago