zslwyuan / Light-HLSLinks
Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
☆62Updated 3 years ago
Alternatives and similar repositories for Light-HLS
Users that are interested in Light-HLS are comparing it to the libraries listed below
Sorting:
- DASS HLS Compiler☆29Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- ☆87Updated last year
- CGRA Compilation Framework☆88Updated 2 years ago
- ☆16Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆59Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- A DSL for Systolic Arrays☆82Updated 6 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- ☆29Updated 8 years ago
- Next generation CGRA generator☆115Updated this week
- ☆101Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- An integrated CGRA design framework☆91Updated 7 months ago
- ☆61Updated this week
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆130Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆15Updated last week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆140Updated 4 months ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 4 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 8 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆70Updated 7 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆78Updated 6 years ago