Alternatives and similar repositories for dataflow_architecture

Users that are interested in dataflow_architecture are comparing it to the libraries listed below

• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆106Updated 7 months ago
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆81Updated 9 months ago
• leesou / H2-LLM-ISCA-2025
  H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference
  ☆78Updated 7 months ago
• scale-snu / attacc_simulator
  ☆115Updated last year
• Zhaoshixin-sky / CIM-MLC
  [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
  ☆45Updated last year
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆21Updated 8 months ago
• sjtu-zhao-lab / pom
  An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
  ☆54Updated last year
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆54Updated 4 years ago
• scalesim-project / scale-sim-v3
  ☆50Updated 2 weeks ago
• SET-Scheduling-Project / SoMa-HPCA2025
  ☆25Updated 9 months ago
• hatsu3 / Sanger
  ☆47Updated 4 years ago
• ConvolutedDog / HyFiSS
  HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs
  ☆39Updated last year
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆69Updated 2 months ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 3 years ago
• pku-liang / TENET
  An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…
  ☆87Updated last year
• arkhadem / aim_simulator
  A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0
  ☆49Updated 4 months ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆66Updated this week
• CLab-HKUST-GZ / micro58-axcore
  ☆28Updated last month
• casys-kaist / NeuPIMs
  NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing
  ☆104Updated last year
• xcw-1010 / HLSPilot
  ☆45Updated last year
• PrincetonUniversity / LLMCompass
  ☆212Updated last month
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆61Updated 8 months ago
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆171Updated 2 weeks ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 5 months ago
• SFU-HiAccel / HiSpMV
  [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS
  ☆18Updated 3 months ago
• PSAL-POSTECH / PyTorchSim
  PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework
  ☆61Updated this week
• fangjh21 / PALM
  PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training
  ☆20Updated last year
• SAITPublic / PIMSimulator
  Processing-In-Memory (PIM) Simulator
  ☆209Updated last year
• hal-uw / cpelide-micro24-artifact
  This GitHub repo contains the artifact for CPElide, which appears at MICRO '24
  ☆12Updated last year
• witmemtech / CIM-Technical-Papers-Collection
  Computing in memory optimizes data handling by performing operations directly in memory, ideal for high-speed data processing needs. This…
  ☆29Updated last year