maestro-project / maestroLinks
An analytical cost model evaluating DNN mappings (dataflows and tiling).
☆221Updated last year
Alternatives and similar repositories for maestro
Users that are interested in maestro are comparing it to the libraries listed below
Sorting:
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆146Updated 2 months ago
- Repository to host and maintain scale-sim-v2 code☆321Updated 3 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆135Updated last month
- RTL implementation of Flex-DPE.☆107Updated 5 years ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆410Updated 2 weeks ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆154Updated last week
- ☆358Updated 2 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- Processing-In-Memory (PIM) Simulator☆179Updated 7 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆239Updated 2 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆110Updated 2 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆177Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆225Updated 4 years ago
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆205Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆148Updated this week
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆86Updated last year
- Simulator for BitFusion☆100Updated 4 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆135Updated 5 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆101Updated 3 months ago
- A co-design architecture on sparse attention☆51Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 4 months ago
- ☆68Updated 5 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- ☆52Updated last year
- ☆16Updated 2 years ago
- A scalable High-Level Synthesis framework on MLIR☆266Updated last year