maestro-project / maestroLinks
An analytical cost model evaluating DNN mappings (dataflows and tiling).
☆241Updated last year
Alternatives and similar repositories for maestro
Users that are interested in maestro are comparing it to the libraries listed below
Sorting:
- Repository to host and maintain SCALE-Sim code☆380Updated last month
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆153Updated 6 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- ☆371Updated 2 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆147Updated 5 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆230Updated 2 years ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆431Updated 2 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆168Updated last month
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆163Updated last week
- Tool for optimize CNN blocking☆94Updated 5 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆113Updated 2 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆254Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆71Updated last month
- Explore the energy-efficient dataflow scheduling for neural networks.☆231Updated 5 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆182Updated last year
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆108Updated 7 months ago
- ☆58Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆42Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆105Updated 7 months ago
- A co-design architecture on sparse attention☆54Updated 4 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆81Updated 8 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆171Updated this week
- ☆71Updated 9 months ago
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆212Updated 2 years ago
- Simulator for BitFusion☆102Updated 5 years ago
- Processing-In-Memory (PIM) Simulator☆208Updated 11 months ago
- A scalable High-Level Synthesis framework on MLIR☆284Updated last year
- CSV spreadsheets and other material for AI accelerator survey papers☆182Updated last week
- ☆42Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago