maestro-project / maestroLinks
An analytical cost model evaluating DNN mappings (dataflows and tiling).
☆217Updated last year
Alternatives and similar repositories for maestro
Users that are interested in maestro are comparing it to the libraries listed below
Sorting:
- Repository to host and maintain scale-sim-v2 code☆302Updated 2 months ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆141Updated 3 weeks ago
- RTL implementation of Flex-DPE.☆103Updated 5 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆132Updated last week
- ☆352Updated 2 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆126Updated 4 months ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆395Updated 2 weeks ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆151Updated last week
- Explore the energy-efficient dataflow scheduling for neural networks.☆225Updated 4 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆109Updated 2 years ago
- Simulator for BitFusion☆100Updated 4 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆177Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆68Updated 3 months ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- Processing-In-Memory (PIM) Simulator☆169Updated 6 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆143Updated this week
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆68Updated 2 weeks ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆237Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆81Updated last month
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆97Updated 2 months ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆215Updated 6 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆65Updated 4 months ago
- CSV spreadsheets and other material for AI accelerator survey papers☆171Updated last year