Alternatives and similar repositories for arena

Users that are interested in arena are comparing it to the libraries listed below

• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated 2 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆59Updated 7 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆30Updated 3 weeks ago
• tancheng / CGRA-Bench
  ☆15Updated 2 years ago
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆21Updated last year
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 3 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆20Updated 8 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆83Updated last year
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆53Updated 2 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆65Updated last month
• lana555 / dynamatic
  ☆86Updated last year
• tukl-msd / DRAMSpec
  A High-Level DRAM Timing, Power and Area Exploration Tool
  ☆28Updated 4 years ago
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆88Updated 2 months ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆79Updated 10 months ago
• pnnl / soda-opt
  ☆44Updated this week
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• cornell-zhang / UniSparse
  Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization
  ☆30Updated 6 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• ecolab-nus / lisa
  A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.
  ☆36Updated 2 years ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆72Updated 3 weeks ago