pnnl / arenaLinks
The programming runtime and interfaces for ARENA.
☆14Updated 4 years ago
Alternatives and similar repositories for arena
Users that are interested in arena are comparing it to the libraries listed below
Sorting:
- A graph linear algebra overlay☆51Updated 2 years ago
- CGRA Compilation Framework☆91Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Updated last year
- CGRA framework with vectorization support.☆43Updated 2 weeks ago
- ☆13Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- ☆60Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆24Updated last year
- ☆18Updated 4 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆19Updated 8 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆24Updated 4 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆21Updated 2 years ago
- ☆62Updated 10 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- The Chronos FPGA Framework to accelerate ordered applications☆22Updated 5 years ago
- ACM TODAES Best Paper Award, 2022☆32Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- ☆10Updated 3 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last month
- ☆24Updated last year
- ☆30Updated 6 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- EQueue Dialect☆42Updated 4 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated last month
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆33Updated last year