pnnl / arenaLinks
The programming runtime and interfaces for ARENA.
☆14Updated 4 years ago
Alternatives and similar repositories for arena
Users that are interested in arena are comparing it to the libraries listed below
Sorting:
- A graph linear algebra overlay☆51Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- CGRA Compilation Framework☆89Updated 2 years ago
- NeuraChip Accelerator Simulator☆15Updated last year
- CGRA framework with vectorization support.☆41Updated this week
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆40Updated 3 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ☆24Updated 5 years ago
- ☆16Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- ☆60Updated 2 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 4 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Updated 8 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆22Updated last year
- ☆13Updated last year
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆20Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- An integrated CGRA design framework☆91Updated 8 months ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- ☆61Updated 8 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- ☆25Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆148Updated last week
- agile hardware-software co-design☆52Updated 4 years ago
- An Open-Source Tool for CGRA Accelerators☆77Updated 3 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago