Alternatives and similar repositories for arena

Users that are interested in arena are comparing it to the libraries listed below

• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated 2 years ago
• Xilinx / merlin-compiler
  ☆58Updated 2 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆29Updated 2 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆87Updated 2 years ago
• hpc-ulisboa / NDPmulator
  A Full-System Framework for Simulating NDP devices from Caches to DRAM
  ☆19Updated last year
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆22Updated 4 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆35Updated this week
• Blaok / fpga-runtime
  ☆12Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• pku-dasys / easymac
  ☆16Updated 3 years ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆20Updated 8 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆63Updated 11 months ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆129Updated 5 years ago
• PrincetonUniversity / MosaicSim
  Heterogeneous simulator for DECADES Project
  ☆32Updated last year
• IntelLabs / t2sp
  Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
  ☆31Updated last year
• UCLA-VAST / HARP
  ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
  ☆21Updated last year
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆21Updated last year
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆84Updated last year
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆69Updated 6 months ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆14Updated last year
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 6 months ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• georgia-tech-synergy-lab / hardtaco-hls
  HLS project modeling various sparse accelerators.
  ☆11Updated 3 years ago
• cornell-zhang / UniSparse
  Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization
  ☆30Updated 10 months ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆81Updated 6 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆59Updated 6 months ago