Alternatives and similar repositories for fluid

Users that are interested in fluid are comparing it to the libraries listed below

• TsaiAnson / verif
  ☆12Updated 4 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆13Updated 6 years ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 3 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 10 years ago
• euphoric-hardware / simcommand
  SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
  ☆14Updated last year
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆40Updated last month
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated 3 weeks ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Updated 5 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• ucb-bar / chisel-awl
  ☆14Updated 4 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 2 weeks ago
• Kuree / hgdb
  Hardware generator debugger
  ☆75Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 3 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• PeterAaser / tdt4255-chisel-intro
  ☆26Updated 4 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 7 months ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago
• zhemao / creek
  A vector processor implemented in Chisel
  ☆21Updated 11 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆31Updated 8 years ago