Fluid Pipelines
☆11May 4, 2018Updated 8 years ago
Alternatives and similar repositories for fluid
Users that are interested in fluid are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- ☆33Jul 28, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 9 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- MCP server for the X (Twitter) API -- give AI agents the ability to post, search, read, and engage on X☆45Mar 24, 2026Updated 2 months ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- ☆12May 20, 2021Updated 5 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- ☆15Oct 24, 2019Updated 6 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆237Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 8 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 7 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- ESESC: A Fast Multicore Simulator☆140Nov 5, 2025Updated 6 months ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Aug 23, 2019Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆105Jun 27, 2022Updated 3 years ago
- An executable specification of the RISCV ISA in L3.☆43Mar 1, 2019Updated 7 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Jul 17, 2016Updated 9 years ago
- Generic Logic Interfacing Project☆49Jul 29, 2020Updated 5 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆92May 12, 2026Updated last week
- A Modeling and Verification Platform for SoCs using ILAs☆82Jul 3, 2024Updated last year
- Useful utilities for BAR projects☆32Jan 3, 2024Updated 2 years ago
- ☆18Jul 12, 2024Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Libre Silicon Compiler☆22Apr 13, 2021Updated 5 years ago
- Chisel implementation of AES☆24Mar 27, 2020Updated 6 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆26Nov 15, 2021Updated 4 years ago
- Online audio file mastering analyzer☆13Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆318Mar 6, 2026Updated 2 months ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Jan 2, 2019Updated 7 years ago
- ☆30Aug 19, 2019Updated 6 years ago