Alternatives and similar repositories for fluid

Users that are interested in fluid are comparing it to the libraries listed below

• TsaiAnson / verif
  ☆12Updated 4 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated 2 years ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 4 years ago
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆13Updated 6 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 2 months ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆60Updated last year
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 11 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 4 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated last month
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆13Updated 10 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆30Updated last month
• ucb-bar / chisel-awl
  ☆13Updated 4 years ago
• euphoric-hardware / simcommand
  SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
  ☆14Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated 2 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆42Updated 2 weeks ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆18Updated 8 years ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆49Updated 2 years ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• zhemao / creek
  A vector processor implemented in Chisel
  ☆21Updated 11 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆32Updated last month
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated last month