ucb-bar / hwacha-templateLinks
Template for projects using the Hwacha data-parallel accelerator
☆34Updated 4 years ago
Alternatives and similar repositories for hwacha-template
Users that are interested in hwacha-template are comparing it to the libraries listed below
Sorting:
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- ☆21Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Public release☆51Updated 5 years ago
- ☆66Updated 3 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- Project repo for the POSH on-chip network generator☆46Updated 2 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- ☆15Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆55Updated 3 years ago
- ☆58Updated 4 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- ☆61Updated this week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆20Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆35Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆25Updated 2 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Updated 5 years ago
- ☆49Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago