Alternatives and similar repositories for rsd

Users that are interested in rsd are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,540Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆716Updated last month
• riscv-software-src / riscv-tests
  ☆1,033Updated 3 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,611Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,423Updated 5 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,053Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,575Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆711Updated 2 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,086Updated last month
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,930Updated 2 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆893Updated 4 years ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆870Updated 5 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,136Updated last month
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,893Updated this week
• vortexgpgpu / vortex
  ☆1,575Updated this week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,362Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,812Updated last week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆716Updated 4 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆603Updated 3 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆845Updated last week
• riscv-non-isa / riscv-arch-test
  ☆572Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆668Updated 2 weeks ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,044Updated this week
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆777Updated this week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆584Updated 11 months ago
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆944Updated 3 weeks ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,287Updated last year
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆372Updated last year
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆563Updated last week