Alternatives and similar repositories for rsd

Users that are interested in rsd are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆904Updated 2 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆744Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆740Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,475Updated 3 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,121Updated 4 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,657Updated last month
• riscv-software-src / riscv-tests
  ☆1,080Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,669Updated 3 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆604Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,002Updated 6 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆901Updated 4 years ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆872Updated 5 years ago
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,669Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,136Updated 5 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,029Updated 2 weeks ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆870Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆723Updated 2 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,189Updated last month
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,102Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆614Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated 3 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆598Updated last year
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,427Updated 3 months ago
• vortexgpgpu / vortex
  ☆1,742Updated this week
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆970Updated 4 months ago
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆492Updated last year
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆512Updated last year
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆667Updated 2 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆496Updated this week
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆810Updated this week