Alternatives and similar repositories for rvx:

Users that are interested in rvx are comparing it to the libraries listed below

• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆206Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 4 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆143Updated 4 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆111Updated 5 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆461Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆174Updated 3 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆317Updated 9 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆223Updated 4 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆268Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆274Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆246Updated last month
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆308Updated 3 months ago
• SpinalHDL / NaxRiscv
  ☆279Updated 2 weeks ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆132Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆231Updated 2 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆326Updated this week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆234Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆186Updated 8 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆249Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆590Updated last week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆169Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆116Updated 4 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆79Updated 3 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆506Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆173Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆85Updated last week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆149Updated this week