Alternatives and similar repositories for riscv-software-list

Users that are interested in riscv-software-list are comparing it to the libraries listed below

• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆887Updated 4 years ago
• riscvarchive / riscv-gcc
  ☆369Updated 2 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆639Updated this week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆487Updated last month
• riscv-collab / riscv-openocd
  Fork of OpenOCD that has RISC-V support
  ☆487Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• riscv-non-isa / riscv-arch-test
  ☆567Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆842Updated last month
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,169Updated 2 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆715Updated 3 months ago
• riscv-software-src / riscv-tests
  ☆1,024Updated last week
• sifiveinc / freedom-u-sdk
  Freedom U Software Development Kit (FUSDK)
  ☆290Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,082Updated last month
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆211Updated last year
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆357Updated 11 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆772Updated this week
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆730Updated 3 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆581Updated 10 months ago
• riscv / riscv-crypto
  RISC-V cryptography extensions standardisation work.
  ☆391Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆342Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 3 weeks ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,570Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆289Updated last year
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆417Updated this week
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆201Updated last year
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆370Updated last year
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 6 months ago
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,035Updated last year