stnolting / neorv32Links
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
☆1,797Updated last week
Alternatives and similar repositories for neorv32
Users that are interested in neorv32 are comparing it to the libraries listed below
Sorting:
- SERV - The SErial RISC-V CPU☆1,611Updated last month
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,812Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆1,093Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,307Updated 3 weeks ago
- A small, light weight, RISC CPU soft core☆1,423Updated 5 months ago
- Linux on LiteX-VexRiscv☆648Updated last week
- Build your hardware, easily!☆3,396Updated this week
- nextpnr portable FPGA place and route tool☆1,468Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,575Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,569Updated last year
- Universal utility for programming FPGA☆1,367Updated this week
- Modular hardware build system☆1,044Updated this week
- 32-bit Superscalar RISC-V CPU☆1,053Updated 3 years ago
- VeeR EH1 core☆884Updated 2 years ago
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆686Updated 5 months ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,089Updated 4 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆668Updated 2 weeks ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,362Updated last week
- Scala based HDL☆1,819Updated this week
- A modern hardware definition language and toolchain based on Python☆1,722Updated last week
- cocotb: Python-based chip (RTL) verification☆2,021Updated last week
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,540Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,086Updated last month
- Verilator open-source SystemVerilog simulator and lint system☆2,986Updated this week
- Send video/audio over HDMI on an FPGA☆1,179Updated last year
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆662Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆924Updated 7 months ago
- Documenting the Xilinx 7-series bit-stream format.☆808Updated last month
- RISC-V CPU Core (RV32IM)☆1,496Updated 3 years ago
- A Python toolbox for building complex digital hardware☆1,288Updated last month