stnolting / neorv32Links
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
☆1,943Updated this week
Alternatives and similar repositories for neorv32
Users that are interested in neorv32 are comparing it to the libraries listed below
Sorting:
- SERV - The SErial RISC-V CPU☆1,723Updated 2 weeks ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,301Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,961Updated 2 weeks ago
- nextpnr portable FPGA place and route tool☆1,581Updated last week
- Universal utility for programming FPGA☆1,506Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,380Updated 2 weeks ago
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆739Updated 11 months ago
- Linux on LiteX-VexRiscv☆676Updated this week
- A small, light weight, RISC CPU soft core☆1,494Updated 3 weeks ago
- Build your hardware, easily!☆3,660Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,719Updated last week
- Documenting the Xilinx 7-series bit-stream format.☆844Updated 6 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,869Updated last year
- An Open-source FPGA IP Generator☆1,034Updated this week
- 32-bit Superscalar RISC-V CPU☆1,160Updated 4 years ago
- Scala based HDL☆1,897Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,739Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,461Updated 5 months ago
- Open Logic FPGA Standard Library☆839Updated this week
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,122Updated 3 months ago
- VeeR EH1 core☆917Updated 2 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆678Updated 5 months ago
- Open source ecosystem for open FPGA boards☆940Updated this week
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆693Updated last week
- A modern hardware definition language and toolchain based on Python☆1,875Updated 2 weeks ago
- Modular hardware build system☆1,116Updated this week
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆611Updated last week
- cocotb: Python-based chip (RTL) verification☆2,201Updated this week
- Send video/audio over HDMI on an FPGA☆1,234Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,140Updated last week