Alternatives and similar repositories for iseedeaduops-poc:

Users that are interested in iseedeaduops-poc are comparing it to the libraries listed below

• CPU-THU / Spectre-V4-ng
  The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…
  ☆18Updated last year
• vusec / tlbdr
  ☆17Updated 2 years ago
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆27Updated 2 years ago
• vul337 / cfi-eval
  ☆22Updated 4 years ago
• FxPiGaAo / Hacky-Racer
  ☆16Updated last year
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• KULeuven-COSIC / PRIME-SCOPE
  The open-source component of Prime+Scope, published at CCS 2021
  ☆30Updated last year
• bu-icsg / PHMon
  This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).
  ☆26Updated 4 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆26Updated 5 years ago
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• fanyao / branchspec
  Proof of concept code for the BranchSpec exploit.
  ☆9Updated 2 years ago
• greenlsi / reload_refresh
  Reload+Refresh PoC
  ☆14Updated 5 years ago
• compsec-snu / specdoctor
  ☆24Updated 2 years ago
• zzrcxb / LLCFeasible
  Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)
  ☆22Updated last month
• vernamlab / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆20Updated 4 years ago
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• PittECEArch / AdversarialPrefetch
  ☆19Updated 2 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆65Updated last month
• isec-tugraz / halfdouble
  ☆15Updated 2 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 3 years ago
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆17Updated 2 months ago
• FPSG-UIUC / augury
  Using Data Memory-Dependent Prefetchers to Leak Data at Rest
  ☆35Updated 2 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 2 months ago
• vusec / fpvi-scsb
  Rage Against The Machine Clear: A Systematic Analysis of Machine Clears and Their Implications for Transient Execution Attacks
  ☆21Updated 3 years ago
• OleksiiOleksenko / SpecFuzz
  A tool for detecting Spectre vulnerabilities through fuzzing
  ☆40Updated 3 years ago
• cispa / regcheck
  Proof-of-concept implementation for the paper "Reviving Meltdown 3a" (ESORICS 2023)
  ☆14Updated last year
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• cispa / Microarchitectural-Hash-Function-Recovery
  Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)
  ☆28Updated last year
• cispa / osiris
  Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)
  ☆57Updated 3 years ago