Alternatives and similar repositories for iseedeaduops-poc:

Users that are interested in iseedeaduops-poc are comparing it to the libraries listed below

• vusec / tlbdr
  ☆18Updated 2 years ago
• CPU-THU / Spectre-V4-ng
  The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…
  ☆18Updated last year
• KULeuven-COSIC / PRIME-SCOPE
  The open-source component of Prime+Scope, published at CCS 2021
  ☆30Updated last year
• bu-icsg / PHMon
  This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).
  ☆26Updated 4 years ago
• compsec-snu / specdoctor
  ☆21Updated last year
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆19Updated 4 years ago
• vul337 / cfi-eval
  ☆22Updated 4 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆26Updated 2 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆26Updated 4 years ago
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆15Updated last month
• fanyao / branchspec
  Proof of concept code for the BranchSpec exploit.
  ☆9Updated 2 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆58Updated 6 months ago
• cispa / Microarchitectural-Hash-Function-Recovery
  Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)
  ☆27Updated last year
• vernamlab / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆20Updated 4 years ago
• greenlsi / reload_refresh
  Reload+Refresh PoC
  ☆14Updated 4 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆20Updated this week
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆21Updated last year
• PittECEArch / AdversarialPrefetch
  ☆19Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆22Updated 4 months ago
• compsec-snu / difuzz-rtl
  ☆80Updated 8 months ago
• hrosier / ripe64
  64-bit port of the RIPE benchmark (buffer overflow attacks). RIPE was originally developed by John Wilander and Nick Nikiforakis and pres…
  ☆20Updated 3 years ago
• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆18Updated 4 years ago
• cispa / osiris
  Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)
  ☆56Updated 3 years ago
• zzrcxb / LLCFeasible
  Open source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)
  ☆21Updated 3 months ago
• cispa / mwait
  Proof-of-concept implementation for the paper "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channel…
  ☆22Updated last year
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆11Updated 3 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆12Updated last year