riscv-admin / uarch-side-channels
☆13Updated 6 months ago
Related projects ⓘ
Alternatives and complementary repositories for uarch-side-channels
- Group administration repository for Tech: IOPMP Task Group☆13Updated 2 weeks ago
- All the tools you need to reproduce the CellIFT paper experiments☆16Updated last month
- RISC-V Security Model☆29Updated 2 months ago
- RISC-V Security HC admin repo☆15Updated last month
- RISC-V IOMMU Demo (Linux & Bao)☆15Updated 11 months ago
- Security Test Benchmark for Computer Architectures☆20Updated this week
- ☆21Updated last year
- Testing processors with Random Instruction Generation☆29Updated last month
- Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data☆20Updated 2 years ago
- A port of the RIPE suite to RISC-V.☆28Updated 6 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆61Updated 5 years ago
- ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.☆14Updated 3 weeks ago
- COATCheck☆12Updated 6 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆54Updated 3 months ago
- HW Design Collateral for Caliptra RoT IP☆75Updated this week
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆22Updated last month
- Medusa Repository: Transynther tool and Medusa Attack☆20Updated 4 years ago
- MIRAGE (USENIX Security 2021)☆11Updated last year
- HW interface for memory caches☆26Updated 4 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆20Updated last year
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆32Updated 2 years ago
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆42Updated this week
- Proof-of-concept implementation for the paper "Indirect Meltdown: Building Novel Side-Channel Attacks from Transient Execution Attacks" (…☆20Updated last year
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆20Updated 2 years ago
- ☆21Updated last month
- C3-Simulator is a Simics-based functional simulator for the X86 C3 processor, including library and kernel support for pointer and data e…☆14Updated 2 weeks ago
- ☆78Updated last year
- ☆18Updated 9 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- CHERI ISA Specification☆23Updated 4 months ago