☆16Nov 28, 2024Updated last year
Alternatives and similar repositories for uarch-side-channels
Users that are interested in uarch-side-channels are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆23Jun 23, 2023Updated 3 years ago
- RISC-V Security HC admin repo☆17Jan 7, 2025Updated last year
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Nov 6, 2019Updated 6 years ago
- Security Test Benchmark for Computer Architectures☆20Oct 27, 2026Updated last week
- ☆14Dec 30, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Input / Output Physical Memory Protection Unit for RISC-V☆17Jul 20, 2023Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆28Jun 25, 2025Updated last year
- ☆13Jun 26, 2022Updated 4 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆16Mar 23, 2022Updated 4 years ago
- Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)☆26Apr 22, 2024Updated 2 years ago
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11Jun 26, 2026Updated 4 months ago
- Run Linux on RISC-V Spike Simulator☆67Oct 22, 2026Updated last week
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆23Aug 22, 2022Updated 4 years ago
- ☆48Dec 19, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data☆22Oct 13, 2022Updated 4 years ago
- This is the main repo for Penglai.☆73Oct 12, 2023Updated 3 years ago
- MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…☆87Jan 24, 2024Updated 2 years ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆144Aug 30, 2024Updated 2 years ago
- A tool for estimating a system's information leakage via Machine Learning☆10Jun 28, 2024Updated 2 years ago
- Enhanced PQOS (Intel RDT Software) with DDIO-related Functionalities☆16May 25, 2022Updated 4 years ago
- ☆15May 30, 2023Updated 3 years ago
- Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…☆16Jan 7, 2022Updated 4 years ago
- Proof-of-concept implementation of the Obelix software hardening framework, based on LLVM.☆12May 22, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- The artifact for SecSMT paper -- Usenix Security 2022☆30Oct 4, 2022Updated 4 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆58Aug 21, 2019Updated 7 years ago
- Proof-of-concept code for the SMoTherSpectre exploit.☆76Nov 12, 2019Updated 6 years ago
- Hardware-assisted Data-flow Isolation☆29Jan 28, 2018Updated 8 years ago
- MIRAGE (USENIX Security 2021)☆15Nov 8, 2023Updated 2 years ago
- ☆18Jun 26, 2025Updated last year
- RISC-V Confidential VM Extension☆19Jan 14, 2026Updated 9 months ago
- ☆90Aug 26, 2025Updated last year
- SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs (ICCAD 2023)☆23Dec 5, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆64Updated this week
- ☆77Jun 14, 2018Updated 8 years ago
- my solution for leetcode☆13May 3, 2016Updated 10 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆62Apr 27, 2020Updated 6 years ago
- ☆21Jun 16, 2026Updated 4 months ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆90Nov 10, 2025Updated 11 months ago
- LLVM Implementation of different ShadowStack schemes for x86_64☆39May 2, 2020Updated 6 years ago