draperlaboratory / hope-RIPELinks
A port of the RIPE suite to RISC-V.
☆29Updated 7 years ago
Alternatives and similar repositories for hope-RIPE
Users that are interested in hope-RIPE are comparing it to the libraries listed below
Sorting:
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Updated 4 years ago
- ☆95Updated last year
- Security Test Benchmark for Computer Architectures☆21Updated last month
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆73Updated 7 months ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆65Updated 6 years ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆112Updated 3 years ago
- ☆87Updated 2 years ago
- ☆25Updated 2 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆27Updated 4 months ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- The SoC used for the beta phase of Hack@DAC 2018.☆17Updated 5 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆22Updated 3 years ago
- All the tools you need to reproduce the CellIFT paper experiments☆22Updated 8 months ago
- ☆35Updated 4 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).☆26Updated 5 years ago
- rv8 benchmark suite☆20Updated 5 years ago
- Implementation of Tagged Memory security policies into Rocket Core☆10Updated 8 years ago
- The MIT Sanctum processor top-level project☆30Updated 5 years ago
- Group administration repository for Tech: IOPMP Task Group☆13Updated 10 months ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆56Updated 6 years ago
- ☆24Updated 6 months ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.☆11Updated 6 years ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆135Updated last year
- ☆18Updated 4 months ago
- CleanupSpec (MICRO-2019)☆16Updated 5 years ago
- New Cache implementation using Gem5☆13Updated 11 years ago
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11Updated last year