Alternatives and similar repositories for hope-RIPE

Users that are interested in hope-RIPE are comparing it to the libraries listed below

• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 3 months ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆17Updated 4 years ago
• compsec-snu / difuzz-rtl
  ☆100Updated last year
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆68Updated 6 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆76Updated 2 months ago
• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆112Updated 3 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆28Updated 6 months ago
• ECLab-ITU / Cache-Side-Channel-Attacks
  This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.
  ☆58Updated 6 years ago
• cwfletcher / stt
  ☆34Updated last month
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆18Updated 5 years ago
• googleinterns / hw-fuzzing
  ☆87Updated 2 years ago
• bu-icsg / PHMon
  This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).
  ☆27Updated 5 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆61Updated 5 years ago
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 4 years ago
• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated last year
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆23Updated 3 years ago
• riscvarchive / security
  RISC-V Security HC admin repo
  ☆18Updated last year
• ESCristiano / BUSted
  BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
  ☆11Updated last year
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆16Updated 5 years ago
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 6 years ago
• larkmjc / rv8-bench
  rv8 benchmark suite
  ☆23Updated 5 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 5 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆22Updated 4 years ago
• nepoche / Flush-Reload
  A flush-reload side channel attack implementation
  ☆55Updated 3 years ago
• saiteja-talluri / Microarchitectural-attacks
  Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.
  ☆11Updated 6 years ago
• KULeuven-COSIC / PRIME-SCOPE
  The open-source component of Prime+Scope, published at CCS 2021
  ☆36Updated 2 years ago
• vusec / tlbdr
  ☆17Updated 3 years ago
• yshalabi / covert-channel-tutorial
  Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…
  ☆52Updated 6 years ago
• comsec-group / cellift-meta
  All the tools you need to reproduce the CellIFT paper experiments
  ☆23Updated 11 months ago