Alternatives and similar repositories for riscv-ctg

Users that are interested in riscv-ctg are comparing it to the libraries listed below

• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 6 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆74Updated last year
• riscvarchive / riscv-CMOs
  ☆90Updated last month
• riscv-software-src / riscv-isac
  ☆32Updated 10 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 10 months ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆103Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 3 months ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated last month
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 10 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 2 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated last month
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆84Updated 4 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• bsc-loca / sargantana
  ☆108Updated last month
• riscv-software-src / riscof
  ☆91Updated last month
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆66Updated last week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated 2 months ago
• riscv / riscv-test-env
  ☆50Updated this week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆129Updated last month
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 4 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆118Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆194Updated last month
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆182Updated 5 months ago