Alternatives and similar repositories for riscv-ctg

Users that are interested in riscv-ctg are comparing it to the libraries listed below

• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 9 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆78Updated last year
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• riscv-software-src / riscv-isac
  ☆33Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆132Updated last week
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆26Updated 2 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated last month
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆151Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆236Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆72Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated 2 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated last month
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆115Updated 5 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆127Updated last week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆133Updated last month
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 4 months ago
• riscv-software-src / riscof
  ☆98Updated 3 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆249Updated last year
• bsc-loca / sargantana
  ☆120Updated 4 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated 2 weeks ago
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆189Updated this week
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆182Updated last year
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆101Updated 7 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆123Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆198Updated 2 months ago