riscv-software-src / riscv-ctgLinks
☆41Updated last year
Alternatives and similar repositories for riscv-ctg
Users that are interested in riscv-ctg are comparing it to the libraries listed below
Sorting:
- pulp_soc is the core building component of PULP based SoCs☆81Updated 10 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆153Updated last year
- ☆33Updated last year
- Simple runtime for Pulp platforms☆50Updated 2 months ago
- ☆89Updated 4 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆111Updated last week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- HW Design Collateral for Caliptra RoT IP☆124Updated this week
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- RISC-V Verification Interface☆136Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- FPGA tool performance profiling☆104Updated last year
- ☆51Updated this week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 4 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆75Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Updated last year
- ☆99Updated 4 months ago
- RISC-V Nox core☆71Updated 5 months ago
- RISC-V System on Chip Template☆160Updated 4 months ago
- Generic Register Interface (contains various adapters)☆134Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- ☆111Updated 2 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago