Alternatives and similar repositories for urvirt

Users that are interested in urvirt are comparing it to the libraries listed below

• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 3 years ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated 2 months ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated 2 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 8 months ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• twd2 / roload
  My DAC '21 work open-sourced.
  ☆14Updated 4 years ago
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆10Updated 3 years ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆15Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆72Updated last week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆32Updated 3 years ago
• monkey2000 / LPi4A-Case
  A 3d printed case design for Lichee Pi 4A
  ☆11Updated 2 years ago
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated 2 years ago
• thu-cs-lab / jieplag
  Plagiarism detection tool in Rust (inspired by Stanford Moss)
  ☆53Updated 2 months ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆25Updated 3 years ago
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆58Updated last year
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 4 years ago
• jwnhy / coffer
  Coffer is a RISC-V trusted execution environment developed in Rust.
  ☆21Updated 3 years ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆32Updated last year
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆20Updated 3 years ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆118Updated last year
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆12Updated 5 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 6 years ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• cogbt / COGBT
  Compile Optimization Guided Binary Translator (using llvm as infrastructure)
  ☆52Updated last year