Alternatives and similar repositories for urvirt:

Users that are interested in urvirt are comparing it to the libraries listed below

• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated last year
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• twd2 / roload
  My DAC '21 work open-sourced.
  ☆14Updated 4 years ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆16Updated 2 years ago
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated 4 months ago
• jiegec / kb
  My knowledge base
  ☆45Updated this week
• CircuitCoder / MeoWave
  ☆10Updated last year
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆23Updated 2 years ago
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• CircuitCoder / cidr-calc
  CIDR union / subtraction
  ☆14Updated last month
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated last year
• monkey2000 / LPi4A-Case
  A 3d printed case design for Lichee Pi 4A
  ☆12Updated last year
• thu-cs-lab / jieplag
  Plagiarism detection tool in Rust (inspired by Stanford Moss)
  ☆50Updated 3 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 5 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆19Updated 3 weeks ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated last year
• CircuitCoder / ld.meow.so
  Toy ELF dynlinker & interp
  ☆10Updated 9 months ago
• Lancern / soda
  Convert shared libraries into relocatable objects
  ☆10Updated last year
• dramforever / opensbi-h
  WIP: A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆37Updated 2 weeks ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆54Updated last year
• chyyuu / zCore-Design
  ☆13Updated 3 years ago
• madsys-dev / syscall_intercept
  The system call intercepting library
  ☆22Updated 2 years ago
• oscomp / proj47-tee-os
  面向可信执行环境的OS。
  ☆12Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆57Updated 3 years ago