Implements kernels with RISC-V Vector
☆22Mar 24, 2023Updated 3 years ago
Alternatives and similar repositories for rvv-kernels
Users that are interested in rvv-kernels are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- Convert shared libraries into relocatable objects☆10Dec 23, 2023Updated 2 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated last month
- Compiling finite generators to digital logic. WIP☆13Aug 24, 2020Updated 5 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT☆37Jun 18, 2025Updated 9 months ago
- A 3d printed case design for Lichee Pi 4A☆11May 13, 2023Updated 2 years ago
- Relaxed Rust (for cats)☆14Nov 20, 2019Updated 6 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30May 14, 2020Updated 5 years ago
- A naive verilog/systemverilog formatter☆21Mar 22, 2025Updated last year
- Remote JTAG server for remote debugging☆44Dec 31, 2025Updated 2 months ago
- Booting multi-processors on x86 bare-metal.☆12Feb 25, 2022Updated 4 years ago
- PKU CompNet'19 Lab 2 - Homebrew TCP☆12Nov 29, 2019Updated 6 years ago
- 开源软件供应链点亮计划 - 暑期2020的主页代码。This repository is the homepage for Open Source Promotion Plan - Summer 2020 built with create-react-app.☆10Aug 28, 2024Updated last year
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- An MLIR-based AI compiler designed for Python frontend to RISC-V DSA☆13Oct 10, 2024Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- Zero-Config Single-Node Workload Manager☆17Jan 5, 2021Updated 5 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Apr 3, 2024Updated last year
- THU Bell on macOS☆28Feb 24, 2020Updated 6 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Mar 10, 2026Updated 2 weeks ago
- Convert regex(es) to dfa.☆14Apr 30, 2021Updated 4 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- Subscribe to updates from people you follow, from any platform to any platform☆14Mar 14, 2026Updated last week
- Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…☆14Jun 29, 2020Updated 5 years ago
- 5级流水线MIPS-lite微系统（北京工业大学计组课设）☆10Oct 1, 2021Updated 4 years ago
- Run wavedrom in typst☆18Apr 9, 2025Updated 11 months ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Jun 9, 2019Updated 6 years ago
- CIDR union / subtraction☆14Mar 13, 2026Updated last week
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 5 months ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆113May 12, 2022Updated 3 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Sep 18, 2024Updated last year
- User-mode trap-and-emulate hypervisor for RISC-V☆14Feb 11, 2022Updated 4 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago