Alternatives and similar repositories for rvv-kernels:

Users that are interested in rvv-kernels are comparing it to the libraries listed below

• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆21Updated 2 months ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆20Updated last month
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 5 months ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated last year
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 9 months ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆23Updated last year
• sequencer / arithmetic
  ☆33Updated last month
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆55Updated last week
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆34Updated last week
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 4 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆14Updated 3 years ago
• cyyself / cpu232
  The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully
  ☆9Updated 4 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆39Updated last year
• shinezyy / gem5-official-old
  ☆17Updated 3 years ago
• CMU-SAFARI / Virtuoso
  Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…
  ☆58Updated 3 weeks ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆28Updated 2 months ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆26Updated last month
• miaochenlu / Gem5_tutorials
  ☆19Updated last year
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆32Updated 2 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated last year