jiegec / rvv-kernelsLinks
Implements kernels with RISC-V Vector
☆22Updated 2 years ago
Alternatives and similar repositories for rvv-kernels
Users that are interested in rvv-kernels are comparing it to the libraries listed below
Sorting:
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- Run Rocket Chip on VCU128☆30Updated 2 months ago
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆37Updated last month
- My RV64 CPU (Work in progress)☆19Updated 3 years ago
- What if everything is a io_uring?☆16Updated 3 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 10 months ago
- Microarchitecture diagrams of several CPUs☆45Updated 2 weeks ago
- The 'missing header' for Chisel☆22Updated 9 months ago
- BOOM's Simulation Accelerator.☆13Updated 4 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated last year
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- CQU Dual Issue Machine☆38Updated last year
- chipyard in mill :P☆77Updated 2 years ago
- ☆17Updated 3 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆48Updated 6 months ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 4 years ago
- ☆17Updated 3 years ago
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10Updated 4 years ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆13Updated 2 years ago
- My knowledge base☆75Updated this week
- ☆21Updated 4 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆34Updated 11 months ago
- ☆15Updated 3 years ago
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆80Updated 2 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆33Updated 4 months ago