riscv / riscv-test-env
☆45Updated 2 months ago
Alternatives and similar repositories for riscv-test-env:
Users that are interested in riscv-test-env are comparing it to the libraries listed below
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- ☆82Updated last month
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 8 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- Provides various testers for chisel users☆100Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆170Updated 7 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆139Updated 3 weeks ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 8 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆155Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆80Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Platform Level Interrupt Controller☆36Updated 10 months ago
- ☆42Updated 3 years ago
- Simple runtime for Pulp platforms☆42Updated this week
- Provides dot visualizations of chisel/firrtl circuits☆118Updated last year
- OmniXtend cache coherence protocol☆78Updated 4 years ago
- RISC-V Frontend Server☆62Updated 5 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago