comparch-security / chipyard-random-llc
A Rocket-Chip with a Dynamically Randomized LLC
☆12Updated 5 months ago
Alternatives and similar repositories for chipyard-random-llc:
Users that are interested in chipyard-random-llc are comparing it to the libraries listed below
- Wrappers for open source FPU hardware implementations.☆30Updated 10 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆14Updated last month
- Implements kernels with RISC-V Vector☆21Updated last year
- Run Rocket Chip on VCU128☆29Updated 2 months ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆19Updated this week
- ☆17Updated 2 years ago
- ☆27Updated 2 months ago
- ☆32Updated this week
- The RTL source for AnyCore RISC-V☆31Updated 2 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 5 years ago
- The 'missing header' for Chisel☆18Updated this week
- A bare-metal application to test specific features of the risc-v hypervisor extension☆36Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆16Updated this week
- An FPGA-based NetTLP adapter☆24Updated 4 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 9 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆32Updated last year
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆11Updated 4 years ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- AIA IP compliant with the RISC-V AIA spec☆35Updated 3 weeks ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- Simple UVM environment for experimenting with Verilator.☆17Updated last month
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆26Updated 5 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆56Updated 3 years ago
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- The official NaplesPU hardware code repository☆15Updated 5 years ago
- This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…☆23Updated this week
- Chisel NVMe controller☆15Updated 2 years ago
- ☆11Updated 2 years ago