comparch-security / chipyard-random-llc

Related projects ⓘ

Alternatives and complementary repositories for chipyard-random-llc

• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆17Updated 2 weeks ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆27Updated 10 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 7 months ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆11Updated this week
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆16Updated 3 weeks ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆54Updated 2 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆29Updated 2 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆34Updated 10 months ago
• chipsalliance / tilelink
  ☆25Updated 9 months ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 2 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• ccelio / riscv-hpmcounters
  A simple utility for doing RISC-V HPM perf monitoring.
  ☆14Updated 7 years ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆10Updated 3 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆31Updated last year
• sifive / riscv-vector-intrinsic-fuzzing
  A random fuzz generator for the RISC-V vector extension intrinsics
  ☆18Updated last week
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆10Updated 5 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• hanhwi / SimPoint
  ☆9Updated 2 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆12Updated 7 months ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆30Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆22Updated last month
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆35Updated 6 months ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated last year
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• nhynes / chisel3-axi
  Chisel3 AXI4-{Lite, Full, Stream} Definitions
  ☆13Updated 5 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆27Updated 6 months ago