CircuitCoder / millLinks
RV32I by cats
☆15Updated 2 years ago
Alternatives and similar repositories for mill
Users that are interested in mill are comparing it to the libraries listed below
Sorting:
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Relaxed Rust (for cats)☆14Updated 5 years ago
- A naive verilog/systemverilog formatter☆21Updated 7 months ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 4 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Updated 3 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Updated 2 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 8 months ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30Updated 5 years ago
- My knowledge base☆72Updated last week
- Run Rocket Chip on VCU128☆30Updated 3 weeks ago
- A router IP written in Verilog.☆12Updated 5 years ago
- Wrappers for open source FPU hardware implementations.☆35Updated last year
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆41Updated 3 months ago
- Dockerfile with Vivado for CI☆27Updated 5 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Updated 3 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- PKU CompNet'19 Lab 2 - Homebrew TCP☆12Updated 5 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- ☆17Updated 3 years ago
- Microarchitecture diagrams of several CPUs☆43Updated last month
- What if everything is a io_uring?☆16Updated 3 years ago
- A 3d printed case design for Lichee Pi 4A☆11Updated 2 years ago
- The 'missing header' for Chisel☆21Updated 7 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last week
- Tsinghua Advanced Networking Labs on FPGA☆38Updated last year