Alternatives and similar repositories for mill

Users that are interested in mill are comparing it to the libraries listed below

• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 4 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 5 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• CircuitCoder / MeowRust
  Relaxed Rust (for cats)
  ☆16Updated 5 years ago
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago
• twd2 / fpga-nat64
  A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.
  ☆31Updated 5 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• jiegec / kb
  My knowledge base
  ☆66Updated last week
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 6 months ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆28Updated 5 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 9 months ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆16Updated 2 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆42Updated this week
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆40Updated last year
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• cnrv / OSEDA
  Open-Source EDA workshop for RISC-V community
  ☆12Updated 3 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆44Updated last year
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 5 months ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated last month
• dramforever / finlog
  Compiling finite generators to digital logic. WIP
  ☆14Updated 5 years ago
• Fugoes / ctrj
  Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…
  ☆15Updated 5 years ago
• revyos / xuantie-c900-bugs
  Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920
  ☆24Updated 2 months ago