RV32I by cats
☆15Sep 4, 2023Updated 3 years ago
Alternatives and similar repositories for mill
Users that are interested in mill are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Compiling finite generators to digital logic. WIP☆13Aug 24, 2020Updated 6 years ago
- Relaxed Rust (for cats)☆14Nov 20, 2019Updated 6 years ago
- Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…☆14Jun 29, 2020Updated 6 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- Booting multi-processors on x86 bare-metal.☆12Feb 25, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 3 years ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Jun 9, 2019Updated 7 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30May 14, 2020Updated 6 years ago
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- A summary of my projects☆48Dec 29, 2025Updated 8 months ago
- A simple USB to UART board designed with KiCad.☆14May 4, 2023Updated 3 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Mar 10, 2026Updated 6 months ago
- Yet Another AsYnc runtime for RuSt.☆33Feb 1, 2020Updated 6 years ago
- Backend & Frontend for JieLabs☆22Mar 3, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A 3d printed case design for Lichee Pi 4A☆11May 13, 2023Updated 3 years ago
- THU Bell on macOS☆28Feb 24, 2020Updated 6 years ago
- rCore_tutorial_tests☆12Aug 8, 2021Updated 5 years ago
- Warning: 🕳 ahead!☆16Jan 8, 2020Updated 6 years ago
- A naive verilog/systemverilog formatter☆22Apr 2, 2026Updated 5 months ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- Convert shared libraries into relocatable objects☆10Dec 23, 2023Updated 2 years ago
- A hand-written recursive decent Verilog parser.☆10Jun 28, 2026Updated 2 months ago
- PKU CompNet'19 Lab 2 - Homebrew TCP☆12Nov 29, 2019Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- 计算机组成原理课程 RISC-V 监控程序,支持 32 位和 64 位☆128Dec 4, 2025Updated 9 months ago
- The system call intercepting library☆23Sep 18, 2022Updated 4 years ago
- A database management system implemented in Rust from scratch.☆20Jul 24, 2021Updated 5 years ago
- Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University☆12Jun 9, 2019Updated 7 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- My RV64 CPU (Work in progress)☆19Dec 22, 2022Updated 3 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- Tsinghua Advanced Networking Labs on FPGA☆41Oct 24, 2024Updated last year
- An implementation of "Efficient Gradient-Domain Compositing Using Quadtrees", SIGGRAPH 2007.☆25Jan 9, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- My DAC '21 work open-sourced.☆14Feb 25, 2021Updated 5 years ago
- Benchmarking a single‑prompt Rust OS kernel implementation, comparing Claude Code Fable, Opus, and Sonnet.☆82Sep 10, 2026Updated last week
- Convert regex(es) to dfa.☆14Apr 30, 2021Updated 5 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 5 years ago
- ☆18Mar 27, 2026Updated 5 months ago
- Subscribe to updates from people you follow, from any platform to any platform☆19May 27, 2026Updated 3 months ago
- Various data structures implementation, in STL style☆11Jul 26, 2021Updated 5 years ago