Alternatives and similar repositories for mill:

Users that are interested in mill are comparing it to the libraries listed below

• CircuitCoder / MeowRust
  Relaxed Rust (for cats)
  ☆16Updated 5 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆60Updated 3 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆20Updated 2 weeks ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆16Updated 2 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆11Updated 5 years ago
• Fugoes / ctrj
  Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…
  ☆15Updated 4 years ago
• CircuitCoder / ld.meow.so
  Toy ELF dynlinker & interp
  ☆10Updated 10 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 11 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆46Updated this week
• KireinaHoro / khtcp
  PKU CompNet'19 Lab 2 - Homebrew TCP
  ☆12Updated 5 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 5 years ago
• Harry-Chen / HERMES
  HERMES: sHallow dirEctory stRucture Many-filE fileSystem
  ☆20Updated 5 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆20Updated last month
• twd2 / fpga-nat64
  A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.
  ☆31Updated 4 years ago
• dtcxzyw / static-key
  Header-only C/C++ static keys to avoid the overhead of conditional branches
  ☆13Updated last year
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆26Updated last week
• jiegec / SPECCPU2017Harmony
  Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT
  ☆12Updated 2 months ago
• CircuitCoder / MeoWave
  ☆10Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 4 months ago
• dramforever / finlog
  Compiling finite generators to digital logic. WIP
  ☆14Updated 4 years ago