CircuitCoder / millLinks
RV32I by cats
☆15Updated 2 years ago
Alternatives and similar repositories for mill
Users that are interested in mill are comparing it to the libraries listed below
Sorting:
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- Relaxed Rust (for cats)☆14Updated 6 years ago
- A naive verilog/systemverilog formatter☆21Updated 9 months ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 4 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- My RV64 CPU (Work in progress)☆19Updated 3 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Updated 3 years ago
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆37Updated last month
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- My knowledge base☆75Updated last week
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30Updated 5 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Updated 2 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 10 months ago
- Run Rocket Chip on VCU128☆30Updated 2 months ago
- Dockerfile with Vivado for CI☆27Updated 5 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- Microarchitecture diagrams of several CPUs☆44Updated last week
- A 3d printed case design for Lichee Pi 4A☆11Updated 2 years ago
- Baremetal softwares for TrivialMIPS platform☆11Updated 6 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated last year
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- What if everything is a io_uring?☆16Updated 3 years ago
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10Updated 4 years ago
- The 'missing header' for Chisel☆22Updated 9 months ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Updated 3 years ago
- A router IP written in Verilog.☆12Updated 6 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- Remote JTAG server for remote debugging☆43Updated last year