Alternatives and similar repositories for ChannelOS

Users that are interested in ChannelOS are comparing it to the libraries listed below

• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆31Updated 3 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• CircuitCoder / ld.meow.so
  Toy ELF dynlinker & interp
  ☆10Updated last year
• rcore-os / x86-smpboot
  Booting multi-processors on x86 bare-metal.
  ☆11Updated 3 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• rcore-os / aCore
  Asynchronous OS kernel written in Rust.
  ☆34Updated 4 years ago
• CircuitCoder / MeoWave
  ☆10Updated last year
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆36Updated last month
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆32Updated last year
• KireinaHoro / khemu
  Binary translation in Rust
  ☆13Updated 4 years ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 6 months ago
• were / bfsh
  Being a full-stack hacker, RISCV, LLVM, and more.
  ☆17Updated 3 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 2 months ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆28Updated 5 years ago
• typekernel / typekernel
  Warning: 🕳 ahead!
  ☆16Updated 5 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆34Updated 3 years ago
• luojia65 / tiaoshi-dashi-sbi
  调试大师：你见过最强的内核调试器
  ☆36Updated 4 years ago
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated last year
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated last year