Alternatives and similar repositories for ChannelOS

Users that are interested in ChannelOS are comparing it to the libraries listed below

• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆32Updated 3 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• jwnhy / coffer
  Coffer is a RISC-V trusted execution environment developed in Rust.
  ☆20Updated 3 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆63Updated 3 years ago
• were / bfsh
  Being a full-stack hacker, RISCV, LLVM, and more.
  ☆18Updated 3 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated last week
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆25Updated 2 years ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated 2 years ago
• efeslab / moesi-prime
  ☆15Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• stemnic / rustyvisor
  Hypervisor written in Rust for the RISC-V 1.0 hypervisor extension
  ☆16Updated 10 months ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆19Updated 8 months ago
• oscomp / proj47-tee-os
  面向可信执行环境的OS。
  ☆12Updated 3 months ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 6 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 8 months ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆32Updated last year
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆34Updated 3 years ago
• MashPlant / decaf-rs
  Framework of pa code for THU compiler principle course.
  ☆13Updated 5 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• efeslab / eecs582
  Course website for Advanced Operating Systems
  ☆13Updated 3 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago