Alternatives and similar repositories for litmus-tests-riscv

Users that are interested in litmus-tests-riscv are comparing it to the libraries listed below

• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆128Updated last week
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆180Updated 6 years ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆103Updated 6 years ago
• riscvarchive / riscv-CMOs
  ☆90Updated 2 weeks ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 2 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆88Updated last week
• riscv / riscv-plic-spec
  PLIC Specification
  ☆146Updated 2 weeks ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆90Updated 2 weeks ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆157Updated 3 years ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆121Updated 9 months ago
• riscv / riscv-aia
  ☆95Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆102Updated last month
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆162Updated 5 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆110Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 4 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year
• sparcians / map
  Modeling Architectural Platform
  ☆202Updated 3 weeks ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆44Updated 7 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated 2 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆155Updated 10 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆53Updated 4 years ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆83Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆153Updated this week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆187Updated last week