Alternatives and similar repositories for riscv-aclint

Users that are interested in riscv-aclint are comparing it to the libraries listed below

• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• riscvarchive / riscv-CMOs
  ☆90Updated last month
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆44Updated 8 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆102Updated last week
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆110Updated 2 years ago
• riscv / riscv-aia
  ☆96Updated last month
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆52Updated 9 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆89Updated 4 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆107Updated last week
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆54Updated 4 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆58Updated 2 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated last month
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆130Updated last week
• riscv / riscv-plic-spec
  PLIC Specification
  ☆148Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• chipsalliance / uvm-verilator
  ☆97Updated 2 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆232Updated 10 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆84Updated 4 years ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆28Updated 3 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated 3 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆90Updated last month
• riscv / riscv-test-env
  ☆50Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆92Updated last week
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆112Updated this week