Alternatives and similar repositories for embench-rt:

Users that are interested in embench-rt are comparing it to the libraries listed below

• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆38Updated 5 months ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆27Updated 6 months ago
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆21Updated 5 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• riscv-non-isa / riscv-semihosting
  ☆28Updated 2 months ago
• bobbl / rudolv
  RISC-V processor
  ☆29Updated 2 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆105Updated 10 years ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆22Updated 2 years ago
• dovebutch / tlv-comp
  ☆27Updated 2 months ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆34Updated 2 years ago
• polarfire-soc / meta-polarfire-soc-yocto-bsp
  PolarFire SoC yocto Board Support Package
  ☆54Updated 3 weeks ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 12 years ago
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆25Updated 4 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆40Updated 3 weeks ago
• AlSaqr-platform / he-soc
  ☆31Updated this week
• litex-hub / wishbone-utils
  Utilities for working with a Wishbone bus in an embedded device
  ☆43Updated last year
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year
• tomverbeure / vexriscv_ocd_blog
  Repo that shows how to use the VexRiscv with OpenOCD and semihosting.
  ☆24Updated 3 years ago