chipsalliance / VeeR-ISS
☆122Updated last year
Related projects ⓘ
Alternatives and complementary repositories for VeeR-ISS
- RISC-V RV64GC emulator designed for RTL co-simulation☆217Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆217Updated 2 weeks ago
- ☆161Updated 11 months ago
- VeeR EL2 Core☆250Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆230Updated this week
- Verilog Configurable Cache☆167Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆266Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆199Updated 4 years ago
- ☆215Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆169Updated 10 months ago
- RISC-V Torture Test☆168Updated 4 months ago
- ☆269Updated 2 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated 3 months ago
- SystemC/TLM-2.0 Co-simulation framework☆222Updated 3 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆148Updated this week
- Ariane is a 6-stage RISC-V CPU☆124Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆177Updated this week
- A Fast, Low-Overhead On-chip Network☆140Updated this week
- RISC-V Formal Verification Framework☆112Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆225Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- Code used in☆174Updated 7 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago
- RiscyOO: RISC-V Out-of-Order Processor☆153Updated 4 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆218Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆195Updated 2 weeks ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆118Updated 5 months ago
- RISC-V Verification Interface☆76Updated 2 months ago
- ☆81Updated 2 years ago