Alternatives and similar repositories for VeeR-ISS:

Users that are interested in VeeR-ISS are comparing it to the libraries listed below

• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆223Updated 4 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆169Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆249Updated 2 weeks ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆186Updated 8 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆174Updated 3 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆85Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆234Updated this week
• chipsalliance / uvm-verilator
  ☆88Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆139Updated 2 weeks ago
• SpinalHDL / NaxRiscv
  ☆279Updated 2 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆68Updated last week
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆132Updated 5 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆173Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆80Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆85Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 4 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆274Updated last year
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆238Updated 4 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆182Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆268Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆99Updated this week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆206Updated last week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆147Updated 4 months ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆156Updated this week
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆146Updated this week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆111Updated 5 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆83Updated last month
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆170Updated 7 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆79Updated last week