Alternatives and similar repositories for riscof

Users that are interested in riscof are comparing it to the libraries listed below

• riscv-ovpsim / imperas-riscv-tests
  ☆193Updated 2 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆257Updated last year
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆205Updated this week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆160Updated 5 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆212Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆138Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆195Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆178Updated 3 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆238Updated last year
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆146Updated this week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆200Updated last week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆317Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆292Updated this week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆223Updated 3 weeks ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 2 months ago
• rafaelcalcada / rvx
  32-bit RISC-V microcontroller for embedded, FPGA and ASIC applications
  ☆189Updated last week
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆153Updated 6 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated 2 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆195Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆305Updated 2 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆150Updated this week
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆286Updated this week
• SpinalHDL / NaxRiscv
  ☆306Updated 2 weeks ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆107Updated this week
• chipsalliance / VeeR-ISS
  ☆151Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆192Updated last week
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆172Updated this week