Alternatives and similar repositories for riscof

Users that are interested in riscof are comparing it to the libraries listed below

• riscv-ovpsim / imperas-riscv-tests
  ☆191Updated 2 years ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆223Updated last month
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆145Updated last week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆199Updated 2 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆250Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆237Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆206Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆189Updated 3 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆153Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆110Updated 2 months ago
• SpinalHDL / NaxRiscv
  ☆301Updated last month
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆169Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆288Updated 2 weeks ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆190Updated 2 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆304Updated 2 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆283Updated this week
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆105Updated last month
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆134Updated 3 weeks ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆150Updated 4 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 4 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆313Updated 2 weeks ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆187Updated 2 weeks ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆98Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆173Updated 2 weeks ago
• riscv / riscv-aia
  ☆98Updated 3 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆134Updated last week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 8 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆134Updated last month