riscv-software-src / riscof
☆77Updated 2 weeks ago
Alternatives and similar repositories for riscof:
Users that are interested in riscof are comparing it to the libraries listed below
- The multi-core cluster of a PULP system.☆89Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆143Updated 5 months ago
- ☆86Updated 2 years ago
- ☆170Updated last year
- RISC-V IOMMU Specification☆112Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆89Updated 3 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 5 months ago
- PLIC Specification☆140Updated 2 years ago
- ☆90Updated last year
- ☆42Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- ☆32Updated 5 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆208Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆143Updated 3 weeks ago
- RISC-V architecture concurrency model litmus tests☆75Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆89Updated 7 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 11 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆103Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆50Updated 2 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 5 months ago
- RISC-V Verification Interface☆87Updated last month
- RISC-V Torture Test☆189Updated 9 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆224Updated 4 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 5 months ago
- Self checking RISC-V directed tests☆103Updated last month
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆264Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 10 months ago
- ☆88Updated 3 weeks ago
- Generic Register Interface (contains various adapters)☆112Updated 6 months ago