riscvarchive / riscv-linux

Related projects ⓘ

Alternatives and complementary repositories for riscv-linux

• riscvarchive / riscv-qemu
  QEMU with RISC-V (RV64G, RV32G) Emulation Support
  ☆387Updated 5 years ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,144Updated last year
• sifive / freedom-e-sdk
  Open Source Software for Developing on the Freedom E Platform - Deprecated
  ☆581Updated 4 months ago
• riscvarchive / riscv-wiki
  ☆250Updated 7 years ago
• riscvarchive / riscv-gcc
  ☆361Updated last year
• sifive / freedom
  Source files for SiFive's Freedom platforms
  ☆1,111Updated 3 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆592Updated last month
• sifive / freedom-u-sdk
  Freedom U Software Development Kit (FUSDK)
  ☆276Updated this week
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆597Updated last year
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆459Updated 3 years ago
• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,433Updated this week
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆855Updated 4 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆836Updated 3 years ago
• riscv-collab / riscv-openocd
  Fork of OpenOCD that has RISC-V support
  ☆452Updated last week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆494Updated 3 weeks ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,736Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆818Updated last year
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆696Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,371Updated last month
• cnrv / home
  为推广RISC-V尽些薄力
  ☆306Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆959Updated 3 months ago
• riscv-software-src / opensbi
  RISC-V Open Source Supervisor Binary Interface
  ☆1,019Updated this week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆457Updated last month
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,273Updated this week
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆394Updated 5 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆687Updated 2 months ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,115Updated 3 weeks ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,251Updated last week
• riscv-software-src / riscv-tests
  ☆891Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆624Updated last week