Alternatives and similar repositories for riscv-angel

Users that are interested in riscv-angel are comparing it to the libraries listed below

• riscvarchive / riscv-qemu
  QEMU with RISC-V (RV64G, RV32G) Emulation Support
  ☆390Updated 6 years ago
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆707Updated 3 years ago
• westerndigitalcorporation / RISC-V-Linux
  This repository provides a Linux kernel bootable on RISC-V boards from SiFive
  ☆169Updated 5 years ago
• marmolejo / zet
  Open source implementation of a x86 processor
  ☆321Updated 7 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆639Updated this week
• riscvarchive / riscv-wiki
  ☆250Updated 8 years ago
• riscvarchive / riscv-gcc
  ☆369Updated 2 years ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆602Updated last year
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆547Updated 2 months ago
• sifiveinc / freedom-u-sdk
  Freedom U Software Development Kit (FUSDK)
  ☆290Updated last month
• riscvarchive / riscv-linux
  RISC-V Linux Port
  ☆609Updated 6 years ago
• riscv-collab / v8
  Port of Google v8 engine to RISC-V.
  ☆240Updated 8 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆370Updated last year
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆445Updated 3 years ago
• antonblanchard / microwatt
  A tiny Open POWER ISA softcore written in VHDL 2008
  ☆686Updated 2 months ago
• riscvarchive / riscv-glibc
  RISC-V port of GNU's libc
  ☆71Updated 4 years ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆772Updated this week
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆238Updated last month
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆149Updated 2 years ago
• Arlet / verilog-6502
  A Verilog HDL model of the MOS 6502 CPU
  ☆343Updated 2 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆325Updated 3 years ago
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆268Updated 10 months ago
• andrescv / jupiter
  RISC-V Assembler and Runtime Simulator
  ☆430Updated last year
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆203Updated 4 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• asicguy / gplgpu
  GPL v3 2D/3D graphics engine in verilog
  ☆667Updated 10 years ago
• zhemao / ez8
  The Easy 8-bit Processor
  ☆183Updated 11 years ago
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆201Updated last year
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆715Updated 3 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆487Updated last month