Alternatives and similar repositories for riscv-qemu:

Users that are interested in riscv-qemu are comparing it to the libraries listed below

• riscvarchive / riscv-linux
  RISC-V Linux Port
  ☆606Updated 5 years ago
• riscvarchive / riscv-wiki
  ☆250Updated 8 years ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆596Updated last year
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆614Updated last month
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,158Updated 2 years ago
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆700Updated 3 years ago
• riscvarchive / riscv-gcc
  ☆369Updated last year
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆407Updated 6 years ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆148Updated 2 years ago
• riscv-collab / riscv-openocd
  Fork of OpenOCD that has RISC-V support
  ☆468Updated this week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆523Updated this week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆478Updated last month
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆165Updated 9 years ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆863Updated 4 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆317Updated 9 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆734Updated this week
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆202Updated 4 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆710Updated 2 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆549Updated this week
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆118Updated last year
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆647Updated 4 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆260Updated 2 weeks ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 2 years ago
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆461Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆862Updated last year
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆321Updated 3 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,028Updated last month
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆943Updated last year
• riscv / riscv-crypto
  RISC-V cryptography extensions standardisation work.
  ☆380Updated last year
• riscv-software-src / riscv-angel
  JavaScript RISC-V ISA Simulator. Boots linux in a web-browser.
  ☆340Updated 4 years ago